From 79252b2ccc626ab0f5796aba253e6cd34bae3c35 Mon Sep 17 00:00:00 2001
From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date: Mon, 18 Feb 2008 17:20:47 +0000
Subject: [PATCH] Modify the artecgroup/dbe61 dts to be equivalent to v2
 Config.lb. The target does not yet compile due to initram breakage, but the
 breakage is really old.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@609 f3766cd6-281f-0410-b1cd-43a5c92072e9
---
 mainboard/artecgroup/dbe61/dts | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts
index 285702b84b..0faa0553f2 100644
--- a/mainboard/artecgroup/dbe61/dts
+++ b/mainboard/artecgroup/dbe61/dts
@@ -84,8 +84,26 @@ end
 		pci@1,0 {
 			/config/("northbridge/amd/geodelx/pci");
 		};
-		pci@1,1 {
+		pci@15,0 {
 			/config/("southbridge/amd/cs5536/dts");
+			/* Interrupt enables for LPC bus.
+			 *  Each bit is an IRQ 0-15. */
+			lpc_serirq_enable = "0x00001002";
+			/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
+			lpc_serirq_polarity = "0x0000effd";
+			/* 0:continuous 1:quiet */
+			lpc_serirq_mode = "1";
+			/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 
+			 * See virtual PIC spec. */
+			enable_gpio_int_route = "0x0D0C0700";
+			/* COM1 settings */
+			com1_enable = "0";
+			com1_address = "0x2f8";
+			com1_irq = "3";
+			/* COM2 settings */
+			com2_enable = "1";
+			com2_address = "0x3f8";
+			com2_irq = "4";
 		};
 	};
 };