Emulation/switch-coreboot
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rework memlayout

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This commit is contained in:
Andre Heider 2018-02-03 22:01:24 +01:00
parent bd9843f6dc
commit 7285eee18b
1 changed files with 32 additions and 1 deletions
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33
src/mainboard/nintendo/switch/memlayout.ld
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@ -1,6 +1,8 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright 2018 Andre Heider <a.heider@gmail.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License. * the Free Software Foundation; version 2 of the License.
@ -11,4 +13,33 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <soc/memlayout.ld> #include <memlayout.h>
#include <rules.h>
#include <arch/header.ld>
/*
* Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
* so the bootblock loading address must be placed after that.
*/
SECTIONS
{
SRAM_START(0x40000000)
#if ENV_ARM64
STACK(0x4000E000, 3K)
#else /* AVP gets a separate stack to avoid any chance of handoff races. */
STACK(0x4000EC00, 3K)
#endif
TIMESTAMP(0x4000F800, 2K)
BOOTBLOCK(0x40010000, 28K)
ROMSTAGE(0x40017000, 56K)
PRERAM_CBMEM_CONSOLE(0x40025000, 8K)
PRERAM_CBFS_CACHE(0x40027000, 100K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
RAMSTAGE(0x80200000, 256K)
POSTRAM_CBFS_CACHE(0xd0000000, 8M)
TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M)
}