From 7285eee18b3fcc85593c3606b47d45bc5b59290b Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Sat, 3 Feb 2018 22:01:24 +0100
Subject: [PATCH] rework memlayout

---
 src/mainboard/nintendo/switch/memlayout.ld | 33 +++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/nintendo/switch/memlayout.ld b/src/mainboard/nintendo/switch/memlayout.ld
index 2c3330651d..0f8214adae 100644
--- a/src/mainboard/nintendo/switch/memlayout.ld
+++ b/src/mainboard/nintendo/switch/memlayout.ld
@@ -1,6 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright 2018 Andre Heider <a.heider@gmail.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -11,4 +13,33 @@
  * GNU General Public License for more details.
  */
 
-#include <soc/memlayout.ld>
+#include <memlayout.h>
+#include <rules.h>
+
+#include <arch/header.ld>
+
+/*
+ * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
+ * so the bootblock loading address must be placed after that.
+ */
+
+SECTIONS
+{
+	SRAM_START(0x40000000)
+#if ENV_ARM64
+	STACK(0x4000E000, 3K)
+#else	/* AVP gets a separate stack to avoid any chance of handoff races. */
+	STACK(0x4000EC00, 3K)
+#endif
+	TIMESTAMP(0x4000F800, 2K)
+	BOOTBLOCK(0x40010000, 28K)
+	ROMSTAGE(0x40017000, 56K)
+	PRERAM_CBMEM_CONSOLE(0x40025000, 8K)
+	PRERAM_CBFS_CACHE(0x40027000, 100K)
+	SRAM_END(0x40040000)
+
+	DRAM_START(0x80000000)
+	RAMSTAGE(0x80200000, 256K)
+	POSTRAM_CBFS_CACHE(0xd0000000, 8M)
+	TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M)
+}