mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Support for gigabit ga-6vxc
This commit is contained in:
Ronald G. Minnich
parent
02d5cb7fb2
commit
620dff9ebb
4 changed files with 714 additions and 0 deletions
245
romimages/RON_GA6-BXC/Makefile
Normal file
245
romimages/RON_GA6-BXC/Makefile
Normal file
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@ -0,0 +1,245 @@
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CPUFLAGS = -DL440BX -DGA6BXC
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CPUFLAGS += -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM
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CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -I$(TOP)/chip/intel -I$(TOP)/linuxbios/include $(BROKEN_GAS)
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DNO_KEYBOARD
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CPUFLAGS += -DINBUF_COPY
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CPUFLAGS += -DPIIX4_DEVFN=0x38
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CFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
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CFLAGS += -DCOPPERMINE
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"'
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LINUX=$(TOP)/../linux-2.4.0-test6.l440gx
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TOP=../..
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INCLUDES=-nostdinc -I $(TOP)/src/include
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CFLAGS=$(INCLUDES) -O2 $(CPUFLAGS) -Ilinux/include -Wall
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OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o
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OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o
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OBJECTS += southbridge.o northbridge.o
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# no supporting C code for this superio (yet)
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# OBJECTS += superio.o
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#OBJECTS += pci.o
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OBJECTS += printk.o vsprintf.o
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OBJECTS += newpci.o linuxpci.o
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OBJECTS += cpuid.o
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OBJECTS += irq_tables.o
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OBJECTS += serial_subr.o
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OBJECTS += mpspec.o
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OBJECTS += microcode.o
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OBJECTS += keyboard.o
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LINK = ld -T $(TOP)/src/mainboard/gigabit/ga-6bxc/ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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all: romimage
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floppy: all
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mcopy -o romimage a:
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# here's the problem: we shouldn't assume we come up with more than
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# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
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# enable all flash and then gunzip the linuxbios. As a result,
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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cp romimage /tmp
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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linuxbios.strip: linuxbios
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objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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linuxbios: $(OBJECTS) vmlinux.bin.gz
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@rm -f biosobject
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$(LINK)
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nm -n linuxbios > linuxbios.map
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DATE="$(shell date)"
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date.h: dummy
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echo "#define DATE \"Compiled: $(DATE)\\r\\n\"" > $@
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dummy:
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# crt0 actually includes .inc files.
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# For self-documenting purposes, we put the FULL PATH of the
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# .inc files (relative to $TOP/src) in crt0.S.
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# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc
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# To make this work, add the extra -I $(TOP)/src here.
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crt0.s: $(TOP)/src/mainboard/gigabit/ga-6bxc/crt0.S date.h
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$(CCASM) -I $(TOP)/src -I. -E $< > crt0.s
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crt0.o : crt0.s
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$(CCASM) -c crt0.s
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mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
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cc $(CFLAGS) -c $<
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mainboard.o: $(TOP)/src/mainboard/gigabit/ga-6bxc/mainboard.c
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cc $(CFLAGS) -c $<
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fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
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cc $(CFLAGS) -c $<
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params.o: $(TOP)/src/lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
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cc $(CFLAGS) -c $<
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southbridge.o: $(TOP)/src/southbridge/intel/piix4e/southbridge.c
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cc $(CFLAGS) -c $<
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northbridge.o: $(TOP)/src/northbridge/intel/440bx/northbridge.c
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cc $(CFLAGS) -c $<
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superio.o: $(TOP)/src/superio/SMC/fdc37n769/superio.c
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cc $(CFLAGS) -c $<
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pci.o: $(TOP)/src/lib/pci.c
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cc $(CFLAGS) -c $<
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irq_tables.o: $(TOP)/src/mainboard/gigabit/ga-6bxc/irq_tables.c
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cc $(CFLAGS) -o $@ -c $<
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mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
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cc $(CFLAGS) -c $<
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subr.o: $(TOP)/src/lib/subr.c
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cc $(CFLAGS) -c $<
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keyboard.o: $(TOP)/src/pc80/keyboard.c
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cc $(CFLAGS) -c $<
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cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
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cc $(CFLAGS) -c $<
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mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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$(CC) $(CFLAGS) -c $<
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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cc $(CFLAGS) -c $<
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vsprintf.o: $(TOP)/src/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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newpci.o: $(TOP)/src/lib/newpci.c
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cc $(CFLAGS) -c $<
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linuxpci.o: $(TOP)/src/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=640k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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vmlinux.bin.gz: vmlinux.bin
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gzip -f -3 vmlinux.bin
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vmlinux.bin: $(LINUX)/vmlinux
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objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
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alltags:
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gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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clean::
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rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
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rm -f a.out *.s *.l
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rm -f TAGS tags
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rm -f docipl
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# here begins stupid stuff for the phlash program. It's ugly.
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#PHLASH_BASE_NAME=p11-0105
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PHLASH_BASE_NAME=p11-0102
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#PHLASH_BASE_NAME=p12-0115
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#PHLASH_BASE_NAME=p13-0125
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phlash: vmlinux.bin.gz linuxbios.rom headers
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rm -f xa?
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split -b 64k vmlinux.bin.gz
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# Now just touch them if we have a really
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# small kernel!
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touch xaa xab xac xad xae xaf xag xah
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# this if starting at bank 4, and proceeding on. Unused banks are dups
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# intel nvram is odd all of the banks are byte swapped
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cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1
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cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3
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cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2
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cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4
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cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7
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cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6
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cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9
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cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8
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cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia
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# Part o & 5 seem not to be written reliably for some reason...
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cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio
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cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5
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sh -x $(TOP)/src/mainboard/gigabit/ga-6bxc/BUILD_PHLASH_FILES $(PHLASH_BASE_NAME)
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headers: \
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$(PHLASH_BASE_NAME).bi1.header \
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$(PHLASH_BASE_NAME).bi2.header \
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$(PHLASH_BASE_NAME).bi3.header \
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$(PHLASH_BASE_NAME).bi4.header \
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$(PHLASH_BASE_NAME).bi5.header \
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$(PHLASH_BASE_NAME).bi6.header \
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$(PHLASH_BASE_NAME).bi7.header \
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$(PHLASH_BASE_NAME).bi8.header \
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$(PHLASH_BASE_NAME).bi9.header \
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$(PHLASH_BASE_NAME).bia.header \
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$(PHLASH_BASE_NAME).bio.header
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# This builds the headers from the intel flash disk.
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# we are not distributing this disk; you need to get it.
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BUILDHEADER=dd if=$< of=$@ bs=1 count=160
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$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio
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$(BUILDHEADER)
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190
src/mainboard/gigabit/ga-6bxc/crt0.S
Normal file
190
src/mainboard/gigabit/ga-6bxc/crt0.S
Normal file
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@ -0,0 +1,190 @@
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/*
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* $ $
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*
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*/
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#include <asm.h>
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#include <intel.h>
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#include <pciconf.h>
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/*
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* This is the entry code (the mkrom(8) utility makes a jumpvector
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* to this adddess.
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*
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* When we get here we are in x86 real mode.
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*
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* %cs = 0xf000 %ip = 0x0000
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* %ds = 0x0000 %es = 0x0000
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* %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6,
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* where x is undefined)
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* %fl = 0x0002
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*/
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.text
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.code16
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/*
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* Putting any code before the gdt tables breaks things
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* because the lgdt instruction is hand assembled/hard coded.
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*/
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#include <cpu/p5/start32.inc>
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jmp 1f
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/* ========================================================== */
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separator: .string "\r\n============================================\r\n"
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greeting: .string "ISR Packbot BIOS.\r\n"
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#include "date.h"
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date: .string DATE
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done: .string "done.\r\n"
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initram: .string "Initializing SDRAM..."
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initdata: .string "Initializing DATA, clearing BSS and STACK..."
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jumpmain: .string "Jumping to intel_main()..."
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delaytest: .string "Delay test... "
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/* ========================================================== */
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1:
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intel_chip_post_macro(0x02)
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#if defined(ITE_SUPER_IO)
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#include <superio/ITE/it8671f/superio.inc>
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#elif defined(SMC_SUPER_IO)
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#include <superio/SMC/fdc37n769/superio.inc>
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#endif
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intel_chip_post_macro(0x03)
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#ifdef SERIAL_CONSOLE
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#include <pc80/serial.inc>
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#endif
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#include <ram/ramtest.inc>
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intel_chip_post_macro(0x04)
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#ifdef SERIAL_CONSOLE
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TTYS0_TX_STRING($separator)
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TTYS0_TX_STRING($greeting)
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TTYS0_TX_STRING($date)
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TTYS0_TX_CHAR($'\n')
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#endif
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intel_chip_post_macro(0x05)
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/* initialize the RAM */
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/* different for each motherboard */
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#include <northbridge/intel/440bx/raminit.inc>
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intel_chip_post_macro(0x20)
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#include <cpu/p6/earlymtrr.inc>
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intel_chip_post_macro(0x21)
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mov $0x00000000, %eax
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mov $0x0009ffff, %ebx
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mov $16, %ecx
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CALLSP(ramtest)
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intel_chip_post_macro(0x23)
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cmp $16, %ecx
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je 1f
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intel_chip_post_macro(0x24)
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jmp .Lhlt
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1:
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intel_chip_post_macro(0x25)
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/* Figure out how much RAM is configured */
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CS_READ($0x67)
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mov $0, %ebx
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mov %al, %bl
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shl $23, %ebx
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sub $1, %ebx
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mov $0x00100000, %eax
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mov $16, %ecx
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CALLSP(ramtest)
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intel_chip_post_macro(0x26)
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|
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cmp $16, %ecx
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je 1f
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intel_chip_post_macro(0x27)
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jmp .Lhlt
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1:
|
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|
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intel_chip_post_macro(0x30)
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|
||||
#ifdef SERIAL_CONSOLE
|
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TTYS0_TX_STRING($initdata)
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#endif
|
||||
|
||||
/*
|
||||
* Copy data into RAM and clear the BSS. Since these segments
|
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* isn't really that big we just copy/clear using bytes, not
|
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* double words.
|
||||
*/
|
||||
|
||||
cld /* clear direction flag */
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leal EXT(_ldata), %esi
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leal EXT(_data), %edi
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movl $EXT(_eldata), %ecx
|
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subl %esi, %ecx
|
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jz .Lnodata /* should not happen */
|
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rep
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movsb
|
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.Lnodata:
|
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intel_chip_post_macro(0x31)
|
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|
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/** clear stack */
|
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xorl %edi, %edi
|
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movl $_PDATABASE, %ecx
|
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xorl %eax, %eax
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rep
|
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stosb
|
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/** clear bss */
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leal EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
|
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subl %edi, %ecx
|
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jz .Lnobss
|
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xorl %eax, %eax
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rep
|
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stosb
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.Lnobss:
|
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|
||||
#ifdef SERIAL_CONSOLE
|
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TTYS0_TX_STRING($done)
|
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#endif
|
||||
intel_chip_post_macro(0x3f)
|
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|
||||
/*
|
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* Now we are finished. Memory is up, data is copied and
|
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* bss is cleared. Now we call the ``main´´ routine and
|
||||
* let it do the rest.
|
||||
*/
|
||||
|
||||
#ifdef SERIAL_CONSOLE
|
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TTYS0_TX_STRING($jumpmain)
|
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#endif
|
||||
|
||||
/* memory is up. Let's do the rest in C -- much easier. */
|
||||
/* set new stack */
|
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movl $_PDATABASE, %esp
|
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call EXT(intel_main)
|
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/*NOTREACHED*/
|
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.Lhlt: hlt
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||||
jmp .Lhlt
|
||||
|
||||
163
src/mainboard/gigabit/ga-6bxc/irq_tables.c
Normal file
163
src/mainboard/gigabit/ga-6bxc/irq_tables.c
Normal file
|
|
@ -0,0 +1,163 @@
|
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|
||||
#include <subr.h>
|
||||
|
||||
/*
|
||||
* This table must be located between 0x000f0000 and 0x000fffff.
|
||||
* By defining it as a const it gets located in the code segment
|
||||
* and therefore inside the necessary 64K block. -tds
|
||||
*/
|
||||
|
||||
#define USB_DEVFN (PIIX4_DEVFN+2)
|
||||
#define SUM_REST 0x00 /* ...just happens to be 0 */
|
||||
#define CHECKSUM (0x00-(SUM_REST+PIIX4_DEVFN+USB_DEVFN))
|
||||
|
||||
// In spite of the comment below I have located this in the
|
||||
// gigabit tree until we work this all out -- RGM
|
||||
/*
|
||||
* This table should work for most systems using the PIIX4
|
||||
* southbridge that have 4 PCI slots.
|
||||
*
|
||||
* I recall that the 440GX board that Ron was using had
|
||||
* the PIIX4 at a different location. This will effect the
|
||||
* devfn of the router and USB controller as well as the
|
||||
* checksum. Hopefully the defines will allow this to
|
||||
* be a bit more portable.
|
||||
* -tds
|
||||
*/
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*5, /* u16 size - size of entire table struct */
|
||||
0, /* u8 rtr_bus - router bus */
|
||||
PIIX4_DEVFN, /* u8 rtr_devfn - router devfn */
|
||||
0x0e00, /* u16 exclusive_irqs - mask of IRQs for PCI use */
|
||||
0x8086, /* u16 rtr_vendor - router vendor id */
|
||||
0x7110, /* u16 rtr_devfn - router device id */
|
||||
0, /* u8 miniport_data - "crap" */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
|
||||
/* struct irq_info slots[0] */
|
||||
{
|
||||
{
|
||||
0, /* u8 bus */
|
||||
USB_DEVFN, /* u8 devfn for USB controller */
|
||||
{
|
||||
{
|
||||
0x00, /* u8 link - IRQ line ID */
|
||||
0x0000, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x00, /* u8 link - IRQ line ID */
|
||||
0x0000, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x00, /* u8 link - IRQ line ID */
|
||||
0x0000, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
0, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x40, /* u8 devfn for PCI slot 1 */
|
||||
{
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
1, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x48, /* u8 devfn for PCI slot 2 */
|
||||
{
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
2, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x50, /* u8 devfn for PCI slot 3 */
|
||||
{
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
3, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
},
|
||||
{
|
||||
0, /* u8 bus */
|
||||
0x58, /* u8 devfn for PCI slot 4 */
|
||||
{
|
||||
{
|
||||
0x63, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x60, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x61, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
},
|
||||
{
|
||||
0x62, /* u8 link - IRQ line ID */
|
||||
0xdef8, /* u16 bitmap - Available IRQs */
|
||||
}
|
||||
},
|
||||
4, /* u8 slot */
|
||||
0, /* u8 rfu */
|
||||
}
|
||||
}
|
||||
};
|
||||
116
src/mainboard/gigabit/ga-6bxc/ldscript.ld
Normal file
116
src/mainboard/gigabit/ga-6bxc/ldscript.ld
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
*/
|
||||
/* oh, barf. This won't work if all you use is .o's. -- RGM */
|
||||
|
||||
/*
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
/*
|
||||
* Memory map:
|
||||
*
|
||||
* 0x00000 (4*4096 bytes) : stack
|
||||
* 0x04000 (4096 bytes) : private data
|
||||
* 0x05000 : data space
|
||||
* 0x90000 : kernel stack
|
||||
* 0xf0000 (64 Kbyte) : EPROM
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is
|
||||
* max for STPC */
|
||||
rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
|
||||
}
|
||||
|
||||
_PDATABASE = 0x04000;
|
||||
_RAMBASE = 0x05000;
|
||||
_KERNSTK = 0x90000;
|
||||
/* should be parameterized but is not, yuck! */
|
||||
/*
|
||||
_ROMBASE = 0xe0000;
|
||||
*/
|
||||
_ROMBASE = 0xf0000;
|
||||
|
||||
/*
|
||||
* Entry point is not really nececary, since the mkrom(8)
|
||||
* tool creates a entry point that jumps to $0xc000:0x0000.
|
||||
*/
|
||||
/* baloney, but ... RGM*/
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS {
|
||||
/*
|
||||
* First we place the code and read only data (typically const declared).
|
||||
* This get placed in rom.
|
||||
*/
|
||||
.text _ROMBASE : {
|
||||
_text = .;
|
||||
*(.text);
|
||||
*(.rodata);
|
||||
_etext = .;
|
||||
}
|
||||
|
||||
_pdata = .;
|
||||
|
||||
/*
|
||||
.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
|
||||
SIZEOF(.rodata)) {
|
||||
*/
|
||||
.pdata _PDATABASE : AT ( _etext ) {
|
||||
*(.pdata);
|
||||
}
|
||||
|
||||
_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
|
||||
|
||||
/*
|
||||
* After the code we place initialized data (typically initialized
|
||||
* global variables). This gets copied into ram by startup code.
|
||||
* __data_start and __data_end shows where in ram this should be placed,
|
||||
* whereas __data_loadstart and __data_loadend shows where in rom to
|
||||
* copy from.
|
||||
*/
|
||||
.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
|
||||
_data = .;
|
||||
*(.data)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.got)
|
||||
_edata = .;
|
||||
}
|
||||
|
||||
_ldata = LOADADDR(.data);
|
||||
_eldata = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
/*
|
||||
* bss does not contain data, it is just a space that should be zero
|
||||
* initialized on startup. (typically uninitialized global variables)
|
||||
* crt0.S fills between __bss_start and __bss_end with zeroes.
|
||||
*/
|
||||
.bss ( ADDR(.data) + SIZEOF(.data) ) : {
|
||||
_bss = .;
|
||||
*(.bss)
|
||||
*(.sbss)
|
||||
*(COMMON)
|
||||
_ebss = .;
|
||||
_heap = .;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This provides the start and end address for the whole image
|
||||
*/
|
||||
_image = LOADADDR(.text);
|
||||
_eimage = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
/* EOF */
|
||||
Loading…
Add table
Reference in a new issue