From 620dff9ebb853448b30df82a55d2bea6044384a4 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 2 Nov 2000 03:34:10 +0000 Subject: [PATCH] Support for gigabit ga-6vxc --- romimages/RON_GA6-BXC/Makefile | 245 +++++++++++++++++++++ src/mainboard/gigabit/ga-6bxc/crt0.S | 190 ++++++++++++++++ src/mainboard/gigabit/ga-6bxc/irq_tables.c | 163 ++++++++++++++ src/mainboard/gigabit/ga-6bxc/ldscript.ld | 116 ++++++++++ 4 files changed, 714 insertions(+) create mode 100644 romimages/RON_GA6-BXC/Makefile create mode 100644 src/mainboard/gigabit/ga-6bxc/crt0.S create mode 100644 src/mainboard/gigabit/ga-6bxc/irq_tables.c create mode 100644 src/mainboard/gigabit/ga-6bxc/ldscript.ld diff --git a/romimages/RON_GA6-BXC/Makefile b/romimages/RON_GA6-BXC/Makefile new file mode 100644 index 0000000000..61e6f6c267 --- /dev/null +++ b/romimages/RON_GA6-BXC/Makefile @@ -0,0 +1,245 @@ +CPUFLAGS = -DL440BX -DGA6BXC +CPUFLAGS += -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM +CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD +CPUFLAGS += -DNEWPCI + +CPUFLAGS += -I$(TOP)/chip/intel -I$(TOP)/linuxbios/include $(BROKEN_GAS) +CPUFLAGS += -DSERIAL_CONSOLE +CPUFLAGS += -DNO_KEYBOARD +CPUFLAGS += -DINBUF_COPY +CPUFLAGS += -DPIIX4_DEVFN=0x38 + +CFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS +CFLAGS += -DCOPPERMINE + +CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"' + +LINUX=$(TOP)/../linux-2.4.0-test6.l440gx + +TOP=../.. +INCLUDES=-nostdinc -I $(TOP)/src/include +CFLAGS=$(INCLUDES) -O2 $(CPUFLAGS) -Ilinux/include -Wall + +OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o +OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o +OBJECTS += southbridge.o northbridge.o +# no supporting C code for this superio (yet) +# OBJECTS += superio.o +#OBJECTS += pci.o +OBJECTS += printk.o vsprintf.o +OBJECTS += newpci.o linuxpci.o +OBJECTS += cpuid.o +OBJECTS += irq_tables.o +OBJECTS += serial_subr.o +OBJECTS += mpspec.o +OBJECTS += microcode.o +OBJECTS += keyboard.o + +LINK = ld -T $(TOP)/src/mainboard/gigabit/ga-6bxc/ldscript.ld -o $@ $(OBJECTS) +CC=cc $(CFLAGS) +CCASM=cc -I$(TOP)/chip/intel $(CFLAGS) + +all: romimage +floppy: all + mcopy -o romimage a: +# here's the problem: we shouldn't assume we come up with more than +# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will +# enable all flash and then gunzip the linuxbios. As a result, +# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom +# at then end. We always copy it to /tmp so that a waiting root shell +# can put it on the floppy (see ROOTDOIT) +romimage: linuxbios.rom vmlinux.bin.gz.block + cat vmlinux.bin.gz.block linuxbios.rom > romimage + cp romimage /tmp + +linuxbios.rom: linuxbios.strip mkrom + ./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip + +linuxbios.strip: linuxbios + objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip + +linuxbios: $(OBJECTS) vmlinux.bin.gz + @rm -f biosobject + $(LINK) + nm -n linuxbios > linuxbios.map + +DATE="$(shell date)" +date.h: dummy + echo "#define DATE \"Compiled: $(DATE)\\r\\n\"" > $@ + +dummy: + + +# crt0 actually includes .inc files. +# For self-documenting purposes, we put the FULL PATH of the +# .inc files (relative to $TOP/src) in crt0.S. +# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc +# To make this work, add the extra -I $(TOP)/src here. +crt0.s: $(TOP)/src/mainboard/gigabit/ga-6bxc/crt0.S date.h + $(CCASM) -I $(TOP)/src -I. -E $< > crt0.s + +crt0.o : crt0.s + $(CCASM) -c crt0.s + +mkrom: $(TOP)/mkrom/mkrom.c + cc -o mkrom $< + +linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c + cc $(CFLAGS) -c $< + +mainboard.o: $(TOP)/src/mainboard/gigabit/ga-6bxc/mainboard.c + cc $(CFLAGS) -c $< + +fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c + cc $(CFLAGS) -c $< + +params.o: $(TOP)/src/lib/params.c + cc $(CFLAGS) $(LINUXINCLUDE) -c $< + +hardwaremain.o: $(TOP)/src/lib/hardwaremain.c + cc $(CFLAGS) -c $< + +southbridge.o: $(TOP)/src/southbridge/intel/piix4e/southbridge.c + cc $(CFLAGS) -c $< + +northbridge.o: $(TOP)/src/northbridge/intel/440bx/northbridge.c + cc $(CFLAGS) -c $< + +superio.o: $(TOP)/src/superio/SMC/fdc37n769/superio.c + cc $(CFLAGS) -c $< + +pci.o: $(TOP)/src/lib/pci.c + cc $(CFLAGS) -c $< + +irq_tables.o: $(TOP)/src/mainboard/gigabit/ga-6bxc/irq_tables.c + cc $(CFLAGS) -o $@ -c $< + + +mtrr.o: $(TOP)/src/cpu/p6/mtrr.c + cc $(CFLAGS) -c $< + +subr.o: $(TOP)/src/lib/subr.c + cc $(CFLAGS) -c $< + +keyboard.o: $(TOP)/src/pc80/keyboard.c + cc $(CFLAGS) -c $< + +cpuid.o: $(TOP)/src/cpu/p5/cpuid.c + cc $(CFLAGS) -c $< + +mpspec.o: $(TOP)/src/cpu/p6/mpspec.c + $(CC) $(CFLAGS) -c $< + +microcode.o: $(TOP)/src/cpu/p6/microcode.c + $(CC) $(CFLAGS) -c $< + +serial_subr.o: $(TOP)/src/lib/serial_subr.c + cc $(CFLAGS) -c $< + +printk.o: $(TOP)/src/lib/printk.c + cc $(CFLAGS) -c $< + +vsprintf.o: $(TOP)/src/lib/vsprintf.c + cc $(CFLAGS) -c $< + +newpci.o: $(TOP)/src/lib/newpci.c + cc $(CFLAGS) -c $< + +linuxpci.o: $(TOP)/src/lib/linuxpci.c + cc $(CFLAGS) -c $< + +vmlinux.bin.gz.block: vmlinux.bin.gz + dd conv=sync bs=640k if=vmlinux.bin.gz of=vmlinux.bin.gz.block +vmlinux.bin.gz: vmlinux.bin + gzip -f -3 vmlinux.bin + +vmlinux.bin: $(LINUX)/vmlinux + objcopy -O binary -R .note -R .comment -S $< vmlinux.bin + +alltags: + gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c + etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c + + +clean:: + rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s + rm -f a.out *.s *.l + rm -f TAGS tags + rm -f docipl + + + + + + +# here begins stupid stuff for the phlash program. It's ugly. + +#PHLASH_BASE_NAME=p11-0105 +PHLASH_BASE_NAME=p11-0102 +#PHLASH_BASE_NAME=p12-0115 +#PHLASH_BASE_NAME=p13-0125 + +phlash: vmlinux.bin.gz linuxbios.rom headers + rm -f xa? + split -b 64k vmlinux.bin.gz +# Now just touch them if we have a really +# small kernel! + touch xaa xab xac xad xae xaf xag xah +# this if starting at bank 4, and proceeding on. Unused banks are dups +# intel nvram is odd all of the banks are byte swapped + cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1 + cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3 + cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2 + cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4 + cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7 + cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6 + cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9 + cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8 + cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia + # Part o & 5 seem not to be written reliably for some reason... + cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio + cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5 + sh -x $(TOP)/src/mainboard/gigabit/ga-6bxc/BUILD_PHLASH_FILES $(PHLASH_BASE_NAME) + +headers: \ + $(PHLASH_BASE_NAME).bi1.header \ + $(PHLASH_BASE_NAME).bi2.header \ + $(PHLASH_BASE_NAME).bi3.header \ + $(PHLASH_BASE_NAME).bi4.header \ + $(PHLASH_BASE_NAME).bi5.header \ + $(PHLASH_BASE_NAME).bi6.header \ + $(PHLASH_BASE_NAME).bi7.header \ + $(PHLASH_BASE_NAME).bi8.header \ + $(PHLASH_BASE_NAME).bi9.header \ + $(PHLASH_BASE_NAME).bia.header \ + $(PHLASH_BASE_NAME).bio.header + +# This builds the headers from the intel flash disk. +# we are not distributing this disk; you need to get it. +BUILDHEADER=dd if=$< of=$@ bs=1 count=160 + +$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio + $(BUILDHEADER) + + + diff --git a/src/mainboard/gigabit/ga-6bxc/crt0.S b/src/mainboard/gigabit/ga-6bxc/crt0.S new file mode 100644 index 0000000000..b2f1c2b210 --- /dev/null +++ b/src/mainboard/gigabit/ga-6bxc/crt0.S @@ -0,0 +1,190 @@ +/* + * $ $ + * + */ + +#include +#include + +#include + +/* + * This is the entry code (the mkrom(8) utility makes a jumpvector + * to this adddess. + * + * When we get here we are in x86 real mode. + * + * %cs = 0xf000 %ip = 0x0000 + * %ds = 0x0000 %es = 0x0000 + * %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6, + * where x is undefined) + * %fl = 0x0002 + */ + .text + .code16 + +/* + * Putting any code before the gdt tables breaks things + * because the lgdt instruction is hand assembled/hard coded. + */ + +#include + + jmp 1f + + /* ========================================================== */ + +separator: .string "\r\n============================================\r\n" +greeting: .string "ISR Packbot BIOS.\r\n" + +#include "date.h" +date: .string DATE + +done: .string "done.\r\n" +initram: .string "Initializing SDRAM..." +initdata: .string "Initializing DATA, clearing BSS and STACK..." +jumpmain: .string "Jumping to intel_main()..." +delaytest: .string "Delay test... " + + /* ========================================================== */ + +1: + + intel_chip_post_macro(0x02) + +#if defined(ITE_SUPER_IO) +#include +#elif defined(SMC_SUPER_IO) +#include +#endif + + intel_chip_post_macro(0x03) + +#ifdef SERIAL_CONSOLE +#include +#endif + +#include + + intel_chip_post_macro(0x04) + +#ifdef SERIAL_CONSOLE + TTYS0_TX_STRING($separator) + TTYS0_TX_STRING($greeting) + TTYS0_TX_STRING($date) + TTYS0_TX_CHAR($'\n') +#endif + intel_chip_post_macro(0x05) + + /* initialize the RAM */ + /* different for each motherboard */ + +#include + + intel_chip_post_macro(0x20) + +#include + + intel_chip_post_macro(0x21) + + mov $0x00000000, %eax + mov $0x0009ffff, %ebx + mov $16, %ecx + + CALLSP(ramtest) + + intel_chip_post_macro(0x23) + + cmp $16, %ecx + je 1f + + intel_chip_post_macro(0x24) + + jmp .Lhlt +1: + + intel_chip_post_macro(0x25) + + /* Figure out how much RAM is configured */ + + CS_READ($0x67) + mov $0, %ebx + mov %al, %bl + shl $23, %ebx + sub $1, %ebx + + mov $0x00100000, %eax + mov $16, %ecx + + CALLSP(ramtest) + + intel_chip_post_macro(0x26) + + cmp $16, %ecx + je 1f + intel_chip_post_macro(0x27) + jmp .Lhlt +1: + + intel_chip_post_macro(0x30) + +#ifdef SERIAL_CONSOLE + TTYS0_TX_STRING($initdata) +#endif + +/* + * Copy data into RAM and clear the BSS. Since these segments + * isn't really that big we just copy/clear using bytes, not + * double words. + */ + + cld /* clear direction flag */ + leal EXT(_ldata), %esi + leal EXT(_data), %edi + movl $EXT(_eldata), %ecx + subl %esi, %ecx + jz .Lnodata /* should not happen */ + rep + movsb +.Lnodata: + intel_chip_post_macro(0x31) + + /** clear stack */ + xorl %edi, %edi + movl $_PDATABASE, %ecx + xorl %eax, %eax + rep + stosb + /** clear bss */ + leal EXT(_bss), %edi + movl $EXT(_ebss), %ecx + subl %edi, %ecx + jz .Lnobss + xorl %eax, %eax + rep + stosb +.Lnobss: + +#ifdef SERIAL_CONSOLE + TTYS0_TX_STRING($done) +#endif + intel_chip_post_macro(0x3f) + +/* + * Now we are finished. Memory is up, data is copied and + * bss is cleared. Now we call the ``main´´ routine and + * let it do the rest. + */ + +#ifdef SERIAL_CONSOLE + TTYS0_TX_STRING($jumpmain) +#endif + +/* memory is up. Let's do the rest in C -- much easier. */ + /* set new stack */ + movl $_PDATABASE, %esp + call EXT(intel_main) + /*NOTREACHED*/ +.Lhlt: hlt + jmp .Lhlt + diff --git a/src/mainboard/gigabit/ga-6bxc/irq_tables.c b/src/mainboard/gigabit/ga-6bxc/irq_tables.c new file mode 100644 index 0000000000..8a8860a602 --- /dev/null +++ b/src/mainboard/gigabit/ga-6bxc/irq_tables.c @@ -0,0 +1,163 @@ + +#include + +/* + * This table must be located between 0x000f0000 and 0x000fffff. + * By defining it as a const it gets located in the code segment + * and therefore inside the necessary 64K block. -tds + */ + +#define USB_DEVFN (PIIX4_DEVFN+2) +#define SUM_REST 0x00 /* ...just happens to be 0 */ +#define CHECKSUM (0x00-(SUM_REST+PIIX4_DEVFN+USB_DEVFN)) + +// In spite of the comment below I have located this in the +// gigabit tree until we work this all out -- RGM +/* + * This table should work for most systems using the PIIX4 + * southbridge that have 4 PCI slots. + * + * I recall that the 440GX board that Ron was using had + * the PIIX4 at a different location. This will effect the + * devfn of the router and USB controller as well as the + * checksum. Hopefully the defines will allow this to + * be a bit more portable. + * -tds + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*5, /* u16 size - size of entire table struct */ + 0, /* u8 rtr_bus - router bus */ + PIIX4_DEVFN, /* u8 rtr_devfn - router devfn */ + 0x0e00, /* u16 exclusive_irqs - mask of IRQs for PCI use */ + 0x8086, /* u16 rtr_vendor - router vendor id */ + 0x7110, /* u16 rtr_devfn - router device id */ + 0, /* u8 miniport_data - "crap" */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */ + /* struct irq_info slots[0] */ + { + { + 0, /* u8 bus */ + USB_DEVFN, /* u8 devfn for USB controller */ + { + { + 0x00, /* u8 link - IRQ line ID */ + 0x0000, /* u16 bitmap - Available IRQs */ + }, + { + 0x00, /* u8 link - IRQ line ID */ + 0x0000, /* u16 bitmap - Available IRQs */ + }, + { + 0x00, /* u8 link - IRQ line ID */ + 0x0000, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 0, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x40, /* u8 devfn for PCI slot 1 */ + { + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 1, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x48, /* u8 devfn for PCI slot 2 */ + { + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 2, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x50, /* u8 devfn for PCI slot 3 */ + { + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 3, /* u8 slot */ + 0, /* u8 rfu */ + }, + { + 0, /* u8 bus */ + 0x58, /* u8 devfn for PCI slot 4 */ + { + { + 0x63, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x60, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x61, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + }, + { + 0x62, /* u8 link - IRQ line ID */ + 0xdef8, /* u16 bitmap - Available IRQs */ + } + }, + 4, /* u8 slot */ + 0, /* u8 rfu */ + } + } +}; diff --git a/src/mainboard/gigabit/ga-6bxc/ldscript.ld b/src/mainboard/gigabit/ga-6bxc/ldscript.ld new file mode 100644 index 0000000000..c1669e1d79 --- /dev/null +++ b/src/mainboard/gigabit/ga-6bxc/ldscript.ld @@ -0,0 +1,116 @@ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * + * $Id$ + * + */ +/* oh, barf. This won't work if all you use is .o's. -- RGM */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* + * Memory map: + * + * 0x00000 (4*4096 bytes) : stack + * 0x04000 (4096 bytes) : private data + * 0x05000 : data space + * 0x90000 : kernel stack + * 0xf0000 (64 Kbyte) : EPROM + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is + * max for STPC */ + rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */ +} + +_PDATABASE = 0x04000; +_RAMBASE = 0x05000; +_KERNSTK = 0x90000; +/* should be parameterized but is not, yuck! */ +/* +_ROMBASE = 0xe0000; + */ +_ROMBASE = 0xf0000; + +/* + * Entry point is not really nececary, since the mkrom(8) + * tool creates a entry point that jumps to $0xc000:0x0000. + */ +/* baloney, but ... RGM*/ +ENTRY(_start) + +SECTIONS { + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text _ROMBASE : { + _text = .; + *(.text); + *(.rodata); + _etext = .; + } + + _pdata = .; + +/* + .pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) + + SIZEOF(.rodata)) { + */ + .pdata _PDATABASE : AT ( _etext ) { + *(.pdata); + } + + _epdata = LOADADDR(.pdata) + SIZEOF(.pdata); + + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) { + _data = .; + *(.data) + *(.sdata) + *(.sdata2) + *(.got) + _edata = .; + } + + _ldata = LOADADDR(.data); + _eldata = LOADADDR(.data) + SIZEOF(.data); + + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between __bss_start and __bss_end with zeroes. + */ + .bss ( ADDR(.data) + SIZEOF(.data) ) : { + _bss = .; + *(.bss) + *(.sbss) + *(COMMON) + _ebss = .; + _heap = .; + } +} + +/* + * This provides the start and end address for the whole image + */ +_image = LOADADDR(.text); +_eimage = LOADADDR(.data) + SIZEOF(.data); + +/* EOF */