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UPSTREAM: mb/lenovo/t430: Fix PCIe hot-plug ports

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Port 0 is connected to SD-card reader.
Don't mark it as hot-plugable.

BUG=none
BRANCH=none
TEST=none

Change-Id: I3f7e4bd05d2619564408514a873d847e44cef5c0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a703393612
Original-Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19928
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/521033
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Patrick Rudolph 2017-05-26 15:26:10 +02:00 • committed by chrome-bot
parent aa9451f084
commit 485efe53c9
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/lenovo/t430/devicetree.cb
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@ -47,7 +47,7 @@ chip northbridge/intel/sandybridge
register "gpi13_routing" = "2"
register "gpi1_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x17"