From 485efe53c944fb9c5492823076758df5609f8bde Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 26 May 2017 15:26:10 +0200 Subject: [PATCH] UPSTREAM: mb/lenovo/t430: Fix PCIe hot-plug ports Port 0 is connected to SD-card reader. Don't mark it as hot-plugable. BUG=none BRANCH=none TEST=none Change-Id: I3f7e4bd05d2619564408514a873d847e44cef5c0 Signed-off-by: Patrick Georgi Original-Commit-Id: a7033936129baff23fd4ad83ca5963795c4c05c6 Original-Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab Original-Signed-off-by: Patrick Rudolph Original-Reviewed-on: https://review.coreboot.org/19928 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Arthur Heymans Reviewed-on: https://chromium-review.googlesource.com/521033 Commit-Ready: Patrick Georgi Tested-by: Patrick Georgi Reviewed-by: Patrick Georgi --- src/mainboard/lenovo/t430/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 86c8756bf3..0a121b70fe 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -47,7 +47,7 @@ chip northbridge/intel/sandybridge register "gpi13_routing" = "2" register "gpi1_routing" = "2" register "p_cnt_throttling_supported" = "1" - register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x17"