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UPSTREAM: payloads: change coreboot to lowercase

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The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

BUG=none
BRANCH=none
TEST=none

Change-Id: I9aeccd7b0dcf3ea7b8801c76251b7409a79b99d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e81ce0483d
Original-Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20028
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/528258
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Martin Roth 2017-06-03 20:00:36 -06:00 • committed by chrome-bot
parent a179b1bd2f
commit 40b55ed909
7 changed files with 9 additions and 9 deletions
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2
payloads/bayou/lzma.c
View file

@ -1,6 +1,6 @@
/* /*
Coreboot interface to memory-saving variant of LZMA decoder coreboot interface to memory-saving variant of LZMA decoder
(C)opyright 2006 Carl-Daniel Hailfinger (C)opyright 2006 Carl-Daniel Hailfinger
Released under the GNU GPL v2 or later Released under the GNU GPL v2 or later

2
payloads/coreinfo/bootlog_module.c
View file

@ -170,7 +170,7 @@ err_free:
static int bootlog_module_redraw(WINDOW *win) static int bootlog_module_redraw(WINDOW *win)
{ {
print_module_title(win, "Coreboot Bootlog"); print_module_title(win, "coreboot Bootlog");
if (!g_buf) { if (!g_buf) {
return -1; return -1;

6
payloads/coreinfo/coreboot_module.c
View file

@ -42,10 +42,10 @@ int coreboot_module_redraw(WINDOW *win)
int row = 2; int row = 2;
int i; int i;
print_module_title(win, "Coreboot Tables"); print_module_title(win, "coreboot Tables");
if (tables_good) { if (tables_good) {
mvwprintw(win, row++, 1, "No Coreboot tables were found"); mvwprintw(win, row++, 1, "No coreboot tables were found");
return 0; return 0;
} }
@ -249,7 +249,7 @@ static int coreboot_module_init(void)
} }
struct coreinfo_module coreboot_module = { struct coreinfo_module coreboot_module = {
.name = "Coreboot", .name = "coreboot",
.init = coreboot_module_init, .init = coreboot_module_init,
.redraw = coreboot_module_redraw, .redraw = coreboot_module_redraw,
}; };

2
payloads/coreinfo/timestamps_module.c
View file

@ -228,7 +228,7 @@ static int timestamps_module_init(void)
static int timestamps_module_redraw(WINDOW *win) static int timestamps_module_redraw(WINDOW *win)
{ {
print_module_title(win, "Coreboot Timestamps"); print_module_title(win, "coreboot Timestamps");
if (!g_buf) if (!g_buf)
return -1; return -1;

2
payloads/external/SeaBIOS/Kconfig vendored
View file

@ -57,7 +57,7 @@ config SEABIOS_VGA_COREBOOT
depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT
bool bool
help help
Coreboot can initialize the GPU of some mainboards. coreboot can initialize the GPU of some mainboards.
After initializing the GPU, the information about it can be passed to the payload. After initializing the GPU, the information about it can be passed to the payload.
Provide an option rom that implements this legacy VGA BIOS compatibility requirement. Provide an option rom that implements this legacy VGA BIOS compatibility requirement.

2
payloads/libpayload/arch/arm64/main.c
View file

@ -64,7 +64,7 @@ static void pre_sysinfo_scan_mmu_setup(void)
mmu_presysinfo_memory_used(start, end - start); mmu_presysinfo_memory_used(start, end - start);
/* /*
* Memory range 2: Coreboot tables * Memory range 2: coreboot tables
* *
* Maximum size is assumed 2 pages in case it crosses the GRANULE_SIZE * Maximum size is assumed 2 pages in case it crosses the GRANULE_SIZE
* boundary * boundary

2
payloads/libpayload/libc/malloc.c
View file

@ -94,7 +94,7 @@ void init_dma_memory(void *start, u32 size)
} }
/* /*
* DMA memory might not be zeroed by Coreboot on stage loading, so make * DMA memory might not be zeroed by coreboot on stage loading, so make
* sure we clear the magic cookie from last boot. * sure we clear the magic cookie from last boot.
*/ */
*(hdrtype_t *)start = 0; *(hdrtype_t *)start = 0;