From 3674dae609bfc1280c2295fd643d717eb0b0e143 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 16 May 2017 08:39:40 +0800 Subject: [PATCH] UPSTREAM: rockchip/rk3399: remove the delay for enabling SSC The hang was caused by deasserting the reset before, it had been delayed 20us fixing the hang issue. So we can remove this delay for now. BUG=none BRANCH=none TEST=none Change-Id: I12d09cd0d25974bbaffaf444f2af4697d85c2648 Signed-off-by: Patrick Georgi Original-Commit-Id: 2684efc49213802dcd36bd9bddd7a69851b8774a Original-Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919 Original-Signed-off-by: Caesar Wang Original-Reviewed-on: https://review.coreboot.org/19699 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel Original-Reviewed-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/508772 Commit-Ready: Patrick Georgi Tested-by: Patrick Georgi Reviewed-by: Patrick Georgi --- src/soc/rockchip/rk3399/clock.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 944ca6f417..7e205d2ba4 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -356,11 +356,6 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) { u32 divval; - /* - * TODO find the root cause why is the delay needed, otherwise sometimes - * hang somewhere with reboot tests. - */ - udelay(30); assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6); /*