mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This is a small HT fixup until HT links get figured out better.
It removes processors from the list of devices on the domain's bus so that pci_scan_bus won't disable them, then scans for them, then puts them back. There are lots of other ways to do this, but this one seemed minimally invasive and ends up with a correct tree. The dts fixups I should have put in with the other K8 patch for the new resource allocator. I went to the v2 Config.lb files and tried to get them as complete as possible. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1109 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson
parent
403cb4754c
commit
33e15e4148
4 changed files with 193 additions and 108 deletions
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@ -66,52 +66,75 @@
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/{
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/{
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device_operations="dbm690t";
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device_operations="dbm690t";
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mainboard_vendor = "AMD";
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mainboard_vendor = "AMD";
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mainboard_name = "Serengeti";
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mainboard_name = "dbm690t";
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cpus { };
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cpus { };
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apic@0 {
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apic@0 {
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};
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};
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domain@0 {
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domain@0 {
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/config/("northbridge/amd/k8/domain");
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/config/("northbridge/amd/k8/domain");
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pci@1,0{
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/* Make sure that the HT device is first; if it isn't found,
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* the rest of the devices won't be found.
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*/
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pci@0 {
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/config/("southbridge/amd/rs690/ht.dts");
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};
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};
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/* guesses; we need a real lspci */
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pci@1{
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pci0@18,0 {
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/config/("southbridge/amd/sb600/pci.dts");
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/config/("northbridge/amd/k8/pci");
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pci@5{
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/* make sure that the ht device is first, as it controls many other things. */
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pci0 {
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/config/("southbridge/amd/rs690/ht.dts");
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};
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pci1{
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/config/("southbridge/amd/rs690/gfx.dts");
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/config/("southbridge/amd/rs690/gfx.dts");
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};
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};
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pci2{
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};
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/config/("southbridge/amd/rs690/pcie.dts");
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pci@6{ /* Port 2 */
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};
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/config/("southbridge/amd/rs690/pcie.dts");
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pci4{
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};
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/config/("southbridge/amd/sb600/hda.dts");
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pci@7{ /* Port 3 */
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};
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/config/("southbridge/amd/rs690/pcie.dts");
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pci5{
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};
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/config/("southbridge/amd/sb600/usb.dts");
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pci@12{
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};
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/config/("southbridge/amd/sb600/hda.dts");
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pci6{
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};
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/config/("southbridge/amd/sb600/usb2.dts");
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pci@13,0{
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/config/("southbridge/amd/sb600/usb.dts");
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};
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pci@13,1{
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/config/("southbridge/amd/sb600/usb.dts");
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};
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pci@13,2{
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/config/("southbridge/amd/sb600/usb.dts");
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};
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pci@13,3{
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/config/("southbridge/amd/sb600/usb.dts");
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};
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pci@13,4{
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/config/("southbridge/amd/sb600/usb.dts");
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};
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pci@13,5{
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/config/("southbridge/amd/sb600/usb2.dts");
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};
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pci@14,0{
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/config/("southbridge/amd/sb600/sm.dts");
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};
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pci@14,1{
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/config/("southbridge/amd/sb600/ide.dts");
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};
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pci@14,2{
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/config/("southbridge/amd/sb600/ac97audio.dts");
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};
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pci@14,3{
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/config/("southbridge/amd/sb600/lpc.dts");
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ioport@2e {
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/config/("superio/ite/it8712f/dts");
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com1enable = "1";
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};
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};
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};
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};
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pci1@18,0 {
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pci@14,4{
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/config/("northbridge/amd/k8/pci");
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/config/("southbridge/amd/sb600/pci.dts");
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};
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};
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pci2@18,0 {
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pci@18,0 {
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/config/("northbridge/amd/k8/pci");
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/config/("northbridge/amd/k8/pci");
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/* just for illustrating link #2 */
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pci@2,0{
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};
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};
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};
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pci@18,1 {};
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pci@18,1 {};
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pci@18,2 {};
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pci@18,2 {};
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pci@18,3 {};
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pci@18,3 {};
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ioport@2e {
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/config/("superio/ite/it8712f/dts");
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com1enable = "1";
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};
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};
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};
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};
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};
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@ -22,75 +22,81 @@
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device_operations="serengeti";
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device_operations="serengeti";
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mainboard_vendor = "AMD";
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mainboard_vendor = "AMD";
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mainboard_name = "Serengeti";
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mainboard_name = "Serengeti";
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subsystem_vendor = "PCI_VENDOR_ID_AMD";
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mainboard_pci_subsystem_vendor = "PCI_VENDOR_ID_AMD";
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subsystem_device = "0x2b80";
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mainboard_pci_subsystem_device = "0x2b80";
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cpus { };
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cpus { };
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apic@0 {
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apic@0 {
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/config/("northbridge/amd/k8/apic");
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/config/("northbridge/amd/k8/apic");
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};
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};
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domain@0 {
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domain@0 {
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/config/("northbridge/amd/k8/domain");
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/config/("northbridge/amd/k8/domain");
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pci_a@0,0 {
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/config/("southbridge/amd/amd8132/pcix.dts");
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};
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pci_a@0,1 {
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/config/("southbridge/amd/amd8132/apic.dts");
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};
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pci_a@1,0 {
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/config/("southbridge/amd/amd8132/pcix.dts");
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};
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pci_a@1,1 {
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/config/("southbridge/amd/amd8132/apic.dts");
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};
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pci@0,0 {
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/config/("southbridge/amd/amd8111/pci.dts");
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pci@0,0{
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/config/("southbridge/amd/amd8111/usb.dts");
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};
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pci@0,1{
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/config/("southbridge/amd/amd8111/usb.dts");
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};
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pci@0,2{
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/config/("southbridge/amd/amd8111/usb2.dts");
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disabled;
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};
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pci@1,0{
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/config/("southbridge/amd/amd8111/nic.dts");
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disabled;
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};
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};
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pci@1,0 {
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/config/("southbridge/amd/amd8111/lpc.dts");
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ioport@2e {
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/config/("superio/winbond/w83627hf/dts");
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kbenable = "1";
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com1enable = "1";
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hwmenable = "1";
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};
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};
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pci@1,1 {
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/config/("southbridge/amd/amd8111/ide.dts");
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ide0_enable = "1";
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ide1_enable = "1";
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};
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pci@1,2 {
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/config/("southbridge/amd/amd8111/smbus.dts");
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};
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pci@1,3 {
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/config/("southbridge/amd/amd8111/acpi.dts");
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};
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pci@1,5 {
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/config/("southbridge/amd/amd8111/ac97audio.dts");
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disabled;
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};
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pci@1,6 {
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/config/("southbridge/amd/amd8111/ac97modem.dts");
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disabled;
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};
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pci@1,7 {
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};
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pci_8@0,0 {
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/config/("southbridge/amd/amd8151/agpbridge.dts");
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};
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pci_8@1,0 {
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/config/("southbridge/amd/amd8151/agpdev.dts");
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};
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pci@18,0 {
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pci@18,0 {
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/config/("northbridge/amd/k8/pci");
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/config/("northbridge/amd/k8/pci");
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pci_a@0,0 {
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/config/("southbridge/amd/amd8132/pcix.dts");
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};
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pci_a@0,1 {
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/config/("southbridge/amd/amd8132/apic.dts");
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};
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pci_a@1,0 {
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/config/("southbridge/amd/amd8132/pcix.dts");
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};
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pci_a@1,1 {
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/config/("southbridge/amd/amd8132/apic.dts");
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};
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pci@0,0 {
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/config/("southbridge/amd/amd8111/pci.dts");
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pci@0,0{
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/config/("southbridge/amd/amd8111/usb.dts");
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};
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pci@0,1{
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/config/("southbridge/amd/amd8111/usb.dts");
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};
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pci@0,2{
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/config/("southbridge/amd/amd8111/usb2.dts");
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disabled;
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};
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pci@1,0{
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/config/("southbridge/amd/amd8111/nic.dts");
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disabled;
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};
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};
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pci@1,0 {
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/config/("southbridge/amd/amd8111/lpc.dts");
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ioport@2e {
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/config/("superio/winbond/w83627hf/dts");
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kbenable = "1";
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com1enable = "1";
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hwmenable = "1";
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};
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};
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pci@1,1 {
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/config/("southbridge/amd/amd8111/ide.dts");
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ide0_enable = "1";
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ide1_enable = "1";
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};
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pci@1,2 {
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/config/("southbridge/amd/amd8111/smbus.dts");
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};
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pci@1,3 {
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/config/("southbridge/amd/amd8111/acpi.dts");
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};
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pci@1,5 {
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/config/("southbridge/amd/amd8111/ac97audio.dts");
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disabled;
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};
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pci@1,6 {
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/config/("southbridge/amd/amd8111/ac97modem.dts");
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disabled;
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};
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pci@1,7 {
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};
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};
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};
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pci@18,1 {};
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pci@18,1 {};
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pci@18,2 {};
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pci@18,2 {};
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@ -101,12 +107,6 @@
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/config/("northbridge/amd/k8/pci");
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/config/("northbridge/amd/k8/pci");
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};
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};
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pci@19,1 {
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pci@19,1 {
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pci@0,0 {
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/config/("southbridge/amd/amd8151/agpbridge.dts");
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};
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pci@1,0 {
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/config/("southbridge/amd/amd8151/agpdev.dts");
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};
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};
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};
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pci@19,2 {};
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pci@19,2 {};
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pci@19,3 {
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pci@19,3 {
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@ -44,20 +44,58 @@
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apic@0 {
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apic@0 {
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};
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};
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domain@0 {
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domain@0 {
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pci@1,0{
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pci@0,0 { /* MCP55 RAM? */
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};
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pci@1,0 {
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/config/("southbridge/nvidia/mcp55/lpc.dts");
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ioport@2e {
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/config/("superio/ite/it8716f/dts");
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com1enable = "1";
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ecenable = "1";
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kbenable = "1";
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mouseenable = "1";
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gpioenable = "1";
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};
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};
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pci@1,1 { /* smbus */
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};
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pci@2,0 { /* usb */
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};
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pci@2,1 { /* usb */
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};
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pci@4,0 {
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/config/("southbridge/nvidia/mcp55/ide.dts");
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ide0_enable = "1";
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};
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pci@5,0 {
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/config/("southbridge/nvidia/mcp55/sata.dts");
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sata0_enable = "1";
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};
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pci@5,1 {
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/config/("southbridge/nvidia/mcp55/sata.dts");
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sata1_enable = "1";
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};
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pci@6,0 { /* PCI */
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};
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pci@6,1 {
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/*/config/("southbridge/nvidia/mcp55/audio.dts"); */
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};
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pci@8,0 {
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/*
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/config/("southbridge/nvidia/mcp55/nic.dts");
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mac_eeprom_smbus = "3";
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mac_eeprom_addr = "0x51";
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*/
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};
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pci@f,0 { /* PCIe */
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};
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};
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pci@18,0 {
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pci@18,0 {
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/config/("northbridge/amd/k8/pci");
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/config/("northbridge/amd/k8/pci");
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pci@0,0 {
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/config/("southbridge/nvidia/mcp55/ide.dts");
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};
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pci@0,1 {
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/config/("southbridge/nvidia/mcp55/sata.dts");
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};
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};
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};
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ioport@2e {
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pci@18,1 {};
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/config/("superio/ite/it8716f/dts");
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pci@18,2 {};
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com1enable = "1";
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pci@18,3 {
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/config/("northbridge/amd/k8/mcf3");
|
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};
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};
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};
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};
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};
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};
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@ -717,6 +717,7 @@ static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
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{
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{
|
||||||
unsigned reg;
|
unsigned reg;
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||||||
int i;
|
int i;
|
||||||
|
struct device *last_dev, *children;
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "%s: %s \n", __func__, dev->dtsname);
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printk(BIOS_DEBUG, "%s: %s \n", __func__, dev->dtsname);
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||||||
|
|
||||||
|
|
@ -746,8 +747,31 @@ static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
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||||||
}
|
}
|
||||||
}
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}
|
||||||
|
|
||||||
|
/* Take processors off the list; we always know what link they're on. */
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||||||
|
for (last_dev = dev->link[0].children; last_dev;
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||||||
|
last_dev = last_dev->sibling)
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||||||
|
if (last_dev && last_dev->sibling == __f0_dev[0])
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||||||
|
last_dev->sibling = NULL;
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||||||
|
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max = amdk8_scan_chains(dev, __f0_dev[0], max);
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max = amdk8_scan_chains(dev, __f0_dev[0], max);
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/* Save non-processor children. */
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children = dev->link[0].children;
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||||||
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||||||
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/* Probe for processors and disable those that don't respond. */
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||||||
|
dev->link[0].children = __f0_dev[0];
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||||||
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pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18,0), 0xff, 0);
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||||||
|
|
||||||
|
/* Add them back to the new end of the list. */
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||||||
|
for (last_dev = children; last_dev && last_dev->sibling;
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||||||
|
last_dev = last_dev->sibling);
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||||||
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||||||
|
if (last_dev) {
|
||||||
|
last_dev->sibling = __f0_dev[0];
|
||||||
|
dev->link[0].children = children;
|
||||||
|
} else
|
||||||
|
dev->link[0].children = __f0_dev[0];
|
||||||
|
|
||||||
return max;
|
return max;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue