From 33e15e41489934761dc8c7ec06662ec1a172dc39 Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Thu, 8 Jan 2009 16:22:39 +0000 Subject: [PATCH] This is a small HT fixup until HT links get figured out better. It removes processors from the list of devices on the domain's bus so that pci_scan_bus won't disable them, then scans for them, then puts them back. There are lots of other ways to do this, but this one seemed minimally invasive and ends up with a correct tree. The dts fixups I should have put in with the other K8 patch for the new resource allocator. I went to the v2 Config.lb files and tried to get them as complete as possible. Signed-off-by: Myles Watson Acked-by: Peter Stuge git-svn-id: svn://coreboot.org/repository/coreboot-v3@1109 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- mainboard/amd/dbm690t/dts | 85 +++++++++++++-------- mainboard/amd/serengeti/dts | 134 +++++++++++++++++----------------- mainboard/gigabyte/m57sli/dts | 58 ++++++++++++--- northbridge/amd/k8/domain.c | 24 ++++++ 4 files changed, 193 insertions(+), 108 deletions(-) diff --git a/mainboard/amd/dbm690t/dts b/mainboard/amd/dbm690t/dts index f9cffdbc6a..1a449ad651 100644 --- a/mainboard/amd/dbm690t/dts +++ b/mainboard/amd/dbm690t/dts @@ -66,52 +66,75 @@ /{ device_operations="dbm690t"; mainboard_vendor = "AMD"; - mainboard_name = "Serengeti"; + mainboard_name = "dbm690t"; cpus { }; apic@0 { }; domain@0 { /config/("northbridge/amd/k8/domain"); - pci@1,0{ + /* Make sure that the HT device is first; if it isn't found, + * the rest of the devices won't be found. + */ + pci@0 { + /config/("southbridge/amd/rs690/ht.dts"); }; - /* guesses; we need a real lspci */ - pci0@18,0 { - /config/("northbridge/amd/k8/pci"); - /* make sure that the ht device is first, as it controls many other things. */ - pci0 { - /config/("southbridge/amd/rs690/ht.dts"); - }; - pci1{ + pci@1{ + /config/("southbridge/amd/sb600/pci.dts"); + pci@5{ /config/("southbridge/amd/rs690/gfx.dts"); }; - pci2{ - /config/("southbridge/amd/rs690/pcie.dts"); - }; - pci4{ - /config/("southbridge/amd/sb600/hda.dts"); - }; - pci5{ - /config/("southbridge/amd/sb600/usb.dts"); - }; - pci6{ - /config/("southbridge/amd/sb600/usb2.dts"); + }; + pci@6{ /* Port 2 */ + /config/("southbridge/amd/rs690/pcie.dts"); + }; + pci@7{ /* Port 3 */ + /config/("southbridge/amd/rs690/pcie.dts"); + }; + pci@12{ + /config/("southbridge/amd/sb600/hda.dts"); + }; + pci@13,0{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,1{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,2{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,3{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,4{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,5{ + /config/("southbridge/amd/sb600/usb2.dts"); + }; + pci@14,0{ + /config/("southbridge/amd/sb600/sm.dts"); + }; + pci@14,1{ + /config/("southbridge/amd/sb600/ide.dts"); + }; + pci@14,2{ + /config/("southbridge/amd/sb600/ac97audio.dts"); + }; + pci@14,3{ + /config/("southbridge/amd/sb600/lpc.dts"); + ioport@2e { + /config/("superio/ite/it8712f/dts"); + com1enable = "1"; }; }; - pci1@18,0 { - /config/("northbridge/amd/k8/pci"); + pci@14,4{ + /config/("southbridge/amd/sb600/pci.dts"); }; - pci2@18,0 { + pci@18,0 { /config/("northbridge/amd/k8/pci"); - /* just for illustrating link #2 */ - pci@2,0{ - }; }; pci@18,1 {}; pci@18,2 {}; pci@18,3 {}; - ioport@2e { - /config/("superio/ite/it8712f/dts"); - com1enable = "1"; - }; }; }; diff --git a/mainboard/amd/serengeti/dts b/mainboard/amd/serengeti/dts index 39a8f20bc7..957e7b712c 100644 --- a/mainboard/amd/serengeti/dts +++ b/mainboard/amd/serengeti/dts @@ -22,75 +22,81 @@ device_operations="serengeti"; mainboard_vendor = "AMD"; mainboard_name = "Serengeti"; - subsystem_vendor = "PCI_VENDOR_ID_AMD"; - subsystem_device = "0x2b80"; + mainboard_pci_subsystem_vendor = "PCI_VENDOR_ID_AMD"; + mainboard_pci_subsystem_device = "0x2b80"; cpus { }; apic@0 { /config/("northbridge/amd/k8/apic"); }; domain@0 { /config/("northbridge/amd/k8/domain"); + pci_a@0,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); + }; + pci_a@0,1 { + /config/("southbridge/amd/amd8132/apic.dts"); + }; + pci_a@1,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); + }; + pci_a@1,1 { + /config/("southbridge/amd/amd8132/apic.dts"); + }; + pci@0,0 { + /config/("southbridge/amd/amd8111/pci.dts"); + pci@0,0{ + /config/("southbridge/amd/amd8111/usb.dts"); + }; + pci@0,1{ + /config/("southbridge/amd/amd8111/usb.dts"); + }; + pci@0,2{ + /config/("southbridge/amd/amd8111/usb2.dts"); + disabled; + }; + pci@1,0{ + /config/("southbridge/amd/amd8111/nic.dts"); + disabled; + }; + }; + pci@1,0 { + /config/("southbridge/amd/amd8111/lpc.dts"); + ioport@2e { + /config/("superio/winbond/w83627hf/dts"); + kbenable = "1"; + com1enable = "1"; + hwmenable = "1"; + }; + }; + pci@1,1 { + /config/("southbridge/amd/amd8111/ide.dts"); + ide0_enable = "1"; + ide1_enable = "1"; + }; + pci@1,2 { + /config/("southbridge/amd/amd8111/smbus.dts"); + }; + pci@1,3 { + /config/("southbridge/amd/amd8111/acpi.dts"); + }; + pci@1,5 { + /config/("southbridge/amd/amd8111/ac97audio.dts"); + disabled; + }; + pci@1,6 { + /config/("southbridge/amd/amd8111/ac97modem.dts"); + disabled; + }; + pci@1,7 { + }; + pci_8@0,0 { + /config/("southbridge/amd/amd8151/agpbridge.dts"); + }; + pci_8@1,0 { + /config/("southbridge/amd/amd8151/agpdev.dts"); + }; pci@18,0 { /config/("northbridge/amd/k8/pci"); - pci_a@0,0 { - /config/("southbridge/amd/amd8132/pcix.dts"); - }; - pci_a@0,1 { - /config/("southbridge/amd/amd8132/apic.dts"); - }; - pci_a@1,0 { - /config/("southbridge/amd/amd8132/pcix.dts"); - }; - pci_a@1,1 { - /config/("southbridge/amd/amd8132/apic.dts"); - }; - pci@0,0 { - /config/("southbridge/amd/amd8111/pci.dts"); - pci@0,0{ - /config/("southbridge/amd/amd8111/usb.dts"); - }; - pci@0,1{ - /config/("southbridge/amd/amd8111/usb.dts"); - }; - pci@0,2{ - /config/("southbridge/amd/amd8111/usb2.dts"); - disabled; - }; - pci@1,0{ - /config/("southbridge/amd/amd8111/nic.dts"); - disabled; - }; - }; - pci@1,0 { - /config/("southbridge/amd/amd8111/lpc.dts"); - ioport@2e { - /config/("superio/winbond/w83627hf/dts"); - kbenable = "1"; - com1enable = "1"; - hwmenable = "1"; - }; - }; - pci@1,1 { - /config/("southbridge/amd/amd8111/ide.dts"); - ide0_enable = "1"; - ide1_enable = "1"; - }; - pci@1,2 { - /config/("southbridge/amd/amd8111/smbus.dts"); - }; - pci@1,3 { - /config/("southbridge/amd/amd8111/acpi.dts"); - }; - pci@1,5 { - /config/("southbridge/amd/amd8111/ac97audio.dts"); - disabled; - }; - pci@1,6 { - /config/("southbridge/amd/amd8111/ac97modem.dts"); - disabled; - }; - pci@1,7 { - }; }; pci@18,1 {}; pci@18,2 {}; @@ -101,12 +107,6 @@ /config/("northbridge/amd/k8/pci"); }; pci@19,1 { - pci@0,0 { - /config/("southbridge/amd/amd8151/agpbridge.dts"); - }; - pci@1,0 { - /config/("southbridge/amd/amd8151/agpdev.dts"); - }; }; pci@19,2 {}; pci@19,3 { diff --git a/mainboard/gigabyte/m57sli/dts b/mainboard/gigabyte/m57sli/dts index d639149b76..14ef364a5a 100644 --- a/mainboard/gigabyte/m57sli/dts +++ b/mainboard/gigabyte/m57sli/dts @@ -44,20 +44,58 @@ apic@0 { }; domain@0 { - pci@1,0{ + pci@0,0 { /* MCP55 RAM? */ + }; + pci@1,0 { + /config/("southbridge/nvidia/mcp55/lpc.dts"); + ioport@2e { + /config/("superio/ite/it8716f/dts"); + com1enable = "1"; + ecenable = "1"; + kbenable = "1"; + mouseenable = "1"; + gpioenable = "1"; + }; + }; + pci@1,1 { /* smbus */ + }; + pci@2,0 { /* usb */ + }; + pci@2,1 { /* usb */ + }; + pci@4,0 { + /config/("southbridge/nvidia/mcp55/ide.dts"); + ide0_enable = "1"; + }; + pci@5,0 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + sata0_enable = "1"; + }; + pci@5,1 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + sata1_enable = "1"; + }; + pci@6,0 { /* PCI */ + }; + pci@6,1 { + /*/config/("southbridge/nvidia/mcp55/audio.dts"); */ + }; + pci@8,0 { + /* + /config/("southbridge/nvidia/mcp55/nic.dts"); + mac_eeprom_smbus = "3"; + mac_eeprom_addr = "0x51"; + */ + }; + pci@f,0 { /* PCIe */ }; pci@18,0 { /config/("northbridge/amd/k8/pci"); - pci@0,0 { - /config/("southbridge/nvidia/mcp55/ide.dts"); - }; - pci@0,1 { - /config/("southbridge/nvidia/mcp55/sata.dts"); - }; }; - ioport@2e { - /config/("superio/ite/it8716f/dts"); - com1enable = "1"; + pci@18,1 {}; + pci@18,2 {}; + pci@18,3 { + /config/("northbridge/amd/k8/mcf3"); }; }; }; diff --git a/northbridge/amd/k8/domain.c b/northbridge/amd/k8/domain.c index 7170f94294..c09774d578 100644 --- a/northbridge/amd/k8/domain.c +++ b/northbridge/amd/k8/domain.c @@ -717,6 +717,7 @@ static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max) { unsigned reg; int i; + struct device *last_dev, *children; printk(BIOS_DEBUG, "%s: %s \n", __func__, dev->dtsname); @@ -746,8 +747,31 @@ static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max) } } + /* Take processors off the list; we always know what link they're on. */ + for (last_dev = dev->link[0].children; last_dev; + last_dev = last_dev->sibling) + if (last_dev && last_dev->sibling == __f0_dev[0]) + last_dev->sibling = NULL; + max = amdk8_scan_chains(dev, __f0_dev[0], max); + /* Save non-processor children. */ + children = dev->link[0].children; + + /* Probe for processors and disable those that don't respond. */ + dev->link[0].children = __f0_dev[0]; + pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18,0), 0xff, 0); + + /* Add them back to the new end of the list. */ + for (last_dev = children; last_dev && last_dev->sibling; + last_dev = last_dev->sibling); + + if (last_dev) { + last_dev->sibling = __f0_dev[0]; + dev->link[0].children = children; + } else + dev->link[0].children = __f0_dev[0]; + return max; }