mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
UPSTREAM: soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 BUG=None BRANCH=None Change-Id: Id56edcf7c9336f3778b3fdbddab8775f5d5974e6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/367393 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
parent
c75a096c3d
commit
2dca83717b
11 changed files with 318 additions and 233 deletions
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@ -34,6 +34,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += chip.c
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ramstage-y += ehci.c
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ramstage-y += ehci.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
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ramstage-y += gpio_i2c.c
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ramstage-y += gpio_i2c.c
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ramstage-y += i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += lpc.c
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@ -117,10 +117,7 @@ static void chip_init(void *chip_info)
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| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
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| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
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/* Perform silicon specific init. */
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/* Perform silicon specific init. */
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if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
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fsp_silicon_init();
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intel_silicon_init();
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else
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fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
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}
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}
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static void pci_domain_set_resources(device_t dev)
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static void pci_domain_set_resources(device_t dev)
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@ -150,12 +147,3 @@ struct chip_operations soc_intel_quark_ops = {
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.init = &chip_init,
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.init = &chip_init,
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.enable_dev = chip_enable_dev,
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.enable_dev = chip_enable_dev,
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};
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};
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void soc_silicon_init_params(SILICON_INIT_UPD *upd)
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{
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}
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void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
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SILICON_INIT_UPD *new)
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{
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}
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35
src/soc/intel/quark/fsp1_1.c
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35
src/soc/intel/quark/fsp1_1.c
Normal file
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@ -0,0 +1,35 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/ramstage.h>
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void fsp_silicon_init(void)
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{
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if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
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intel_silicon_init();
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else
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fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
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}
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void soc_silicon_init_params(SILICON_INIT_UPD *upd)
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{
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}
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void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
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SILICON_INIT_UPD *new)
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{
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}
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@ -24,6 +24,7 @@ struct chipset_power_state {
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uint32_t prev_sleep_state;
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uint32_t prev_sleep_state;
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} __attribute__ ((packed));
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} __attribute__ ((packed));
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struct chipset_power_state *get_power_state(void);
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struct chipset_power_state *fill_power_state(void);
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struct chipset_power_state *fill_power_state(void);
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#endif
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#endif
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@ -23,5 +23,6 @@
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#include <soc/QuarkNcSocId.h>
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#include <soc/QuarkNcSocId.h>
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void mainboard_gpio_i2c_init(device_t dev);
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void mainboard_gpio_i2c_init(device_t dev);
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void fsp_silicon_init(void);
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#endif /* _SOC_RAMSTAGE_H_ */
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#endif /* _SOC_RAMSTAGE_H_ */
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@ -26,6 +26,8 @@
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#include <soc/reg_access.h>
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#include <soc/reg_access.h>
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asmlinkage void *car_stage_c_entry(void);
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asmlinkage void *car_stage_c_entry(void);
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void clear_smi_and_wake_events(void);
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void disable_rom_shadow(void);
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void report_platform_info(void);
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void report_platform_info(void);
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int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
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int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
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void pcie_init(void);
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void pcie_init(void);
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@ -13,7 +13,9 @@
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# GNU General Public License for more details.
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# GNU General Public License for more details.
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#
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#
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romstage-y += car.c
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romstage-y += car_stage_entry.S
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romstage-y += car_stage_entry.S
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romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
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romstage-y += mtrr.c
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romstage-y += mtrr.c
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romstage-y += pcie.c
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romstage-y += pcie.c
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romstage-y += report_platform.c
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romstage-y += report_platform.c
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67
src/soc/intel/quark/romstage/car.c
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67
src/soc/intel/quark/romstage/car.c
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@ -0,0 +1,67 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/reg_access.h>
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static const struct reg_script legacy_gpio_init[] = {
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/* Temporarily enable the legacy GPIO controller */
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REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
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| LEGACY_GPIO_BASE_ADDRESS),
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/* Temporarily enable the GPE controller */
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REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
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| GPE0_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
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REG_SCRIPT_END
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};
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static const struct reg_script i2c_gpio_controller_init[] = {
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/* Temporarily enable the GPIO controller */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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static const struct reg_script hsuart_init[] = {
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/* Enable the HSUART */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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void car_soc_pre_console_init(void)
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{
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/* Initialize the controllers */
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reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
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reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
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/* Enable the HSUART */
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if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0))
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reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
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if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
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reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
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}
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void car_soc_post_console_init(void)
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{
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report_platform_info();
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};
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199
src/soc/intel/quark/romstage/fsp1_1.c
Normal file
199
src/soc/intel/quark/romstage/fsp1_1.c
Normal file
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@ -0,0 +1,199 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <cbfs.h>
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#include "../chip.h"
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#include <fsp/util.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <string.h>
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asmlinkage void *car_stage_c_entry(void)
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{
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FSP_INFO_HEADER *fih;
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struct cache_as_ram_params car_params = {0};
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void *top_of_stack;
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post_code(0x20);
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/* Copy the FSP binary into ESRAM */
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memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC,
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0x00040000);
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/* Locate the FSP header in ESRAM */
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fih = find_fsp(CONFIG_FSP_ESRAM_LOC);
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/* Start the early verstage/romstage code */
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post_code(0x2A);
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car_params.fih = fih;
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top_of_stack = cache_as_ram_main(&car_params);
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/* Initialize MTRRs and switch stacks after RAM initialized */
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return top_of_stack;
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}
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static struct chipset_power_state power_state CAR_GLOBAL;
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struct chipset_power_state *get_power_state(void)
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{
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return (struct chipset_power_state *)car_get_var_ptr(&power_state);
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}
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struct chipset_power_state *fill_power_state(void)
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{
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struct chipset_power_state *ps = get_power_state();
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ps->prev_sleep_state = 0;
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printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state);
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return ps;
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}
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/* Initialize the UPD parameters for MemoryInit */
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void soc_memory_init_params(struct romstage_params *params,
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MEMORY_INIT_UPD *upd)
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{
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const struct device *dev;
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const struct soc_intel_quark_config *config;
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char *rmu_file;
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size_t rmu_file_len;
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/* Locate the configuration data from devicetree.cb */
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dev = dev_find_slot(0, LPC_DEV_FUNC);
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if (!dev) {
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printk(BIOS_CRIT,
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"Error! Device (PCI:0:%02x.%01x) not found, "
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"soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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return;
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}
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config = dev->chip_info;
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/* Clear SMI and wake events */
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clear_smi_and_wake_events();
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/* Locate the RMU data file in flash */
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rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW,
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&rmu_file_len);
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if (!rmu_file)
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die("Microcode file (rmu.bin) not found.");
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/* Update the UPD data for MemoryInit */
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upd->AddrMode = config->AddrMode;
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upd->ChanMask = config->ChanMask;
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upd->ChanWidth = config->ChanWidth;
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upd->DramDensity = config->DramDensity;
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upd->DramRonVal = config->DramRonVal;
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upd->DramRttNomVal = config->DramRttNomVal;
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upd->DramRttWrVal = config->DramRttWrVal;
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upd->DramSpeed = config->DramSpeed;
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upd->DramType = config->DramType;
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upd->DramWidth = config->DramWidth;
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upd->EccScrubBlkSize = config->EccScrubBlkSize;
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upd->EccScrubInterval = config->EccScrubInterval;
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upd->Flags = config->Flags;
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upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
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upd->RankMask = config->RankMask;
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upd->RmuBaseAddress = (uintptr_t)rmu_file;
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upd->RmuLength = rmu_file_len;
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upd->SerialPortBaseAddress = UART_BASE_ADDRESS;
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upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->SmmTsegSize : 0;
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upd->SocRdOdtVal = config->SocRdOdtVal;
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upd->SocWrRonVal = config->SocWrRonVal;
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upd->SocWrSlewRate = config->SocWrSlewRate;
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upd->SrInt = config->SrInt;
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upd->SrTemp = config->SrTemp;
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upd->tCL = config->tCL;
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upd->tFAW = config->tFAW;
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upd->tRAS = config->tRAS;
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upd->tRRD = config->tRRD;
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upd->tWTR = config->tWTR;
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}
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void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
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MEMORY_INIT_UPD *new)
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{
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/* Display the parameters for MemoryInit */
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printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
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fsp_display_upd_value("AddrMode", sizeof(old->AddrMode),
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old->AddrMode, new->AddrMode);
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fsp_display_upd_value("ChanMask", sizeof(old->ChanMask),
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old->ChanMask, new->ChanMask);
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fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth),
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old->ChanWidth, new->ChanWidth);
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fsp_display_upd_value("DramDensity", sizeof(old->DramDensity),
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old->DramDensity, new->DramDensity);
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fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal),
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old->DramRonVal, new->DramRonVal);
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fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal),
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||||||
|
old->DramRttNomVal, new->DramRttNomVal);
|
||||||
|
fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal),
|
||||||
|
old->DramRttWrVal, new->DramRttWrVal);
|
||||||
|
fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed),
|
||||||
|
old->DramSpeed, new->DramSpeed);
|
||||||
|
fsp_display_upd_value("DramType", sizeof(old->DramType),
|
||||||
|
old->DramType, new->DramType);
|
||||||
|
fsp_display_upd_value("DramWidth", sizeof(old->DramWidth),
|
||||||
|
old->DramWidth, new->DramWidth);
|
||||||
|
fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize),
|
||||||
|
old->EccScrubBlkSize, new->EccScrubBlkSize);
|
||||||
|
fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval),
|
||||||
|
old->EccScrubInterval, new->EccScrubInterval);
|
||||||
|
fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags,
|
||||||
|
new->Flags);
|
||||||
|
fsp_display_upd_value("FspReservedMemoryLength",
|
||||||
|
sizeof(old->FspReservedMemoryLength),
|
||||||
|
old->FspReservedMemoryLength, new->FspReservedMemoryLength);
|
||||||
|
fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask,
|
||||||
|
new->RankMask);
|
||||||
|
fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress),
|
||||||
|
old->RmuBaseAddress, new->RmuBaseAddress);
|
||||||
|
fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
|
||||||
|
old->RmuLength, new->RmuLength);
|
||||||
|
fsp_display_upd_value("SerialPortBaseAddress",
|
||||||
|
sizeof(old->SerialPortBaseAddress),
|
||||||
|
old->SerialPortBaseAddress, new->SerialPortBaseAddress);
|
||||||
|
fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
|
||||||
|
old->SmmTsegSize, new->SmmTsegSize);
|
||||||
|
fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
|
||||||
|
old->SocRdOdtVal, new->SocRdOdtVal);
|
||||||
|
fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal),
|
||||||
|
old->SocWrRonVal, new->SocWrRonVal);
|
||||||
|
fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate),
|
||||||
|
old->SocWrSlewRate, new->SocWrSlewRate);
|
||||||
|
fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt,
|
||||||
|
new->SrInt);
|
||||||
|
fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp,
|
||||||
|
new->SrTemp);
|
||||||
|
fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL);
|
||||||
|
fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW);
|
||||||
|
fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS);
|
||||||
|
fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD);
|
||||||
|
fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR);
|
||||||
|
}
|
||||||
|
|
||||||
|
void soc_after_ram_init(struct romstage_params *params)
|
||||||
|
{
|
||||||
|
/* Disable the ROM shadow 0x000e0000 - 0x000fffff */
|
||||||
|
disable_rom_shadow();
|
||||||
|
|
||||||
|
/* Initialize the PCIe bridges */
|
||||||
|
pcie_init();
|
||||||
|
}
|
|
@ -19,7 +19,7 @@
|
||||||
#include <cpu/x86/mtrr.h>
|
#include <cpu/x86/mtrr.h>
|
||||||
#include <soc/intel/common/util.h>
|
#include <soc/intel/common/util.h>
|
||||||
#include <soc/pci_devs.h>
|
#include <soc/pci_devs.h>
|
||||||
#include <soc/romstage.h>
|
#include <soc/reg_access.h>
|
||||||
|
|
||||||
asmlinkage void *soc_set_mtrrs(void *top_of_stack)
|
asmlinkage void *soc_set_mtrrs(void *top_of_stack)
|
||||||
{
|
{
|
||||||
|
|
|
@ -17,21 +17,14 @@
|
||||||
|
|
||||||
#include <arch/early_variables.h>
|
#include <arch/early_variables.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
#include <cbfs.h>
|
|
||||||
#include "../chip.h"
|
|
||||||
#include <device/pci_def.h>
|
|
||||||
#include <fsp/car.h>
|
|
||||||
#include <fsp/util.h>
|
#include <fsp/util.h>
|
||||||
#include <lib.h>
|
#include <lib.h>
|
||||||
#include <soc/intel/common/util.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
#include <soc/pci_devs.h>
|
#include <soc/pci_devs.h>
|
||||||
#include <soc/pm.h>
|
#include <soc/pm.h>
|
||||||
#include <soc/romstage.h>
|
#include <soc/romstage.h>
|
||||||
#include <soc/reg_access.h>
|
#include <soc/reg_access.h>
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
static const struct reg_script clear_smi_and_wake_events[] = {
|
static const struct reg_script clear_smi_and_wake_events_script[] = {
|
||||||
/* Clear any SMI or wake events */
|
/* Clear any SMI or wake events */
|
||||||
REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S),
|
REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S),
|
||||||
REG_GPE0_READ(R_QNC_GPE0BLK_SMIS),
|
REG_GPE0_READ(R_QNC_GPE0BLK_SMIS),
|
||||||
|
@ -40,221 +33,20 @@ static const struct reg_script clear_smi_and_wake_events[] = {
|
||||||
REG_SCRIPT_END
|
REG_SCRIPT_END
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct reg_script legacy_gpio_init[] = {
|
void clear_smi_and_wake_events(void)
|
||||||
/* Temporarily enable the legacy GPIO controller */
|
|
||||||
REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
|
|
||||||
| LEGACY_GPIO_BASE_ADDRESS),
|
|
||||||
/* Temporarily enable the GPE controller */
|
|
||||||
REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
|
|
||||||
| GPE0_BASE_ADDRESS),
|
|
||||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
|
|
||||||
REG_SCRIPT_END
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct reg_script i2c_gpio_controller_init[] = {
|
|
||||||
/* Temporarily enable the GPIO controller */
|
|
||||||
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
|
|
||||||
REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
|
|
||||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
|
|
||||||
REG_SCRIPT_END
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct reg_script hsuart_init[] = {
|
|
||||||
/* Enable the HSUART */
|
|
||||||
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
|
|
||||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
|
|
||||||
REG_SCRIPT_END
|
|
||||||
};
|
|
||||||
|
|
||||||
asmlinkage void *car_stage_c_entry(void)
|
|
||||||
{
|
{
|
||||||
post_code(0x20);
|
struct chipset_power_state *ps;
|
||||||
if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) {
|
|
||||||
FSP_INFO_HEADER *fih;
|
|
||||||
struct cache_as_ram_params car_params = {0};
|
|
||||||
void *top_of_stack;
|
|
||||||
|
|
||||||
/* Copy the FSP binary into ESRAM */
|
|
||||||
memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC,
|
|
||||||
0x00040000);
|
|
||||||
|
|
||||||
/* Locate the FSP header in ESRAM */
|
|
||||||
fih = find_fsp(CONFIG_FSP_ESRAM_LOC);
|
|
||||||
|
|
||||||
/* Start the early verstage/romstage code */
|
|
||||||
post_code(0x2A);
|
|
||||||
car_params.fih = fih;
|
|
||||||
top_of_stack = cache_as_ram_main(&car_params);
|
|
||||||
|
|
||||||
/* Initialize MTRRs and switch stacks after RAM initialized */
|
|
||||||
return top_of_stack;
|
|
||||||
}
|
|
||||||
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
void car_soc_pre_console_init(void)
|
|
||||||
{
|
|
||||||
/* Initialize the controllers */
|
|
||||||
reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
|
|
||||||
reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
|
|
||||||
|
|
||||||
/* Enable the HSUART */
|
|
||||||
if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0))
|
|
||||||
reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
|
|
||||||
if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
|
|
||||||
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
|
|
||||||
}
|
|
||||||
|
|
||||||
void car_soc_post_console_init(void)
|
|
||||||
{
|
|
||||||
report_platform_info();
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct chipset_power_state power_state CAR_GLOBAL;
|
|
||||||
|
|
||||||
struct chipset_power_state *fill_power_state(void)
|
|
||||||
{
|
|
||||||
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
|
|
||||||
|
|
||||||
ps->prev_sleep_state = ACPI_S0;
|
|
||||||
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
|
|
||||||
return ps;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Initialize the UPD parameters for MemoryInit */
|
|
||||||
void soc_memory_init_params(struct romstage_params *params,
|
|
||||||
MEMORY_INIT_UPD *upd)
|
|
||||||
{
|
|
||||||
const struct device *dev;
|
|
||||||
const struct soc_intel_quark_config *config;
|
|
||||||
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
|
|
||||||
char *rmu_file;
|
|
||||||
size_t rmu_file_len;
|
|
||||||
|
|
||||||
/* Locate the configuration data from devicetree.cb */
|
|
||||||
dev = dev_find_slot(0, LPC_DEV_FUNC);
|
|
||||||
if (!dev) {
|
|
||||||
printk(BIOS_ERR,
|
|
||||||
"Error! Device (PCI:0:%02x.%01x) not found, "
|
|
||||||
"soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC,
|
|
||||||
PCI_FUNCTION_NUMBER_QNC_LPC);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
config = dev->chip_info;
|
|
||||||
|
|
||||||
/* Display the ROM shadow data */
|
|
||||||
hexdump((void *)0x000ffff0, 0x10);
|
|
||||||
|
|
||||||
/* Clear SMI and wake events */
|
/* Clear SMI and wake events */
|
||||||
if (ps->prev_sleep_state != ACPI_S3) {
|
ps = get_power_state();
|
||||||
|
if (ps->prev_sleep_state != 3) {
|
||||||
printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
|
printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
|
||||||
reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events);
|
reg_script_run_on_dev(LPC_BDF,
|
||||||
|
clear_smi_and_wake_events_script);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Locate the RMU data file in flash */
|
|
||||||
rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW,
|
|
||||||
&rmu_file_len);
|
|
||||||
if (!rmu_file)
|
|
||||||
die("Microcode file (rmu.bin) not found.");
|
|
||||||
|
|
||||||
/* Update the UPD data for MemoryInit */
|
|
||||||
printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd);
|
|
||||||
upd->AddrMode = config->AddrMode;
|
|
||||||
upd->ChanMask = config->ChanMask;
|
|
||||||
upd->ChanWidth = config->ChanWidth;
|
|
||||||
upd->DramDensity = config->DramDensity;
|
|
||||||
upd->DramRonVal = config->DramRonVal;
|
|
||||||
upd->DramRttNomVal = config->DramRttNomVal;
|
|
||||||
upd->DramRttWrVal = config->DramRttWrVal;
|
|
||||||
upd->DramSpeed = config->DramSpeed;
|
|
||||||
upd->DramType = config->DramType;
|
|
||||||
upd->DramWidth = config->DramWidth;
|
|
||||||
upd->EccScrubBlkSize = config->EccScrubBlkSize;
|
|
||||||
upd->EccScrubInterval = config->EccScrubInterval;
|
|
||||||
upd->Flags = config->Flags;
|
|
||||||
upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
|
|
||||||
upd->RankMask = config->RankMask;
|
|
||||||
upd->RmuBaseAddress = (uintptr_t)rmu_file;
|
|
||||||
upd->RmuLength = rmu_file_len;
|
|
||||||
upd->SerialPortBaseAddress = UART_BASE_ADDRESS;
|
|
||||||
upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
|
|
||||||
config->SmmTsegSize : 0;
|
|
||||||
upd->SocRdOdtVal = config->SocRdOdtVal;
|
|
||||||
upd->SocWrRonVal = config->SocWrRonVal;
|
|
||||||
upd->SocWrSlewRate = config->SocWrSlewRate;
|
|
||||||
upd->SrInt = config->SrInt;
|
|
||||||
upd->SrTemp = config->SrTemp;
|
|
||||||
upd->tCL = config->tCL;
|
|
||||||
upd->tFAW = config->tFAW;
|
|
||||||
upd->tRAS = config->tRAS;
|
|
||||||
upd->tRRD = config->tRRD;
|
|
||||||
upd->tWTR = config->tWTR;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
|
void disable_rom_shadow(void)
|
||||||
MEMORY_INIT_UPD *new)
|
|
||||||
{
|
|
||||||
/* Display the parameters for MemoryInit */
|
|
||||||
printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
|
|
||||||
fsp_display_upd_value("AddrMode", sizeof(old->AddrMode),
|
|
||||||
old->AddrMode, new->AddrMode);
|
|
||||||
fsp_display_upd_value("ChanMask", sizeof(old->ChanMask),
|
|
||||||
old->ChanMask, new->ChanMask);
|
|
||||||
fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth),
|
|
||||||
old->ChanWidth, new->ChanWidth);
|
|
||||||
fsp_display_upd_value("DramDensity", sizeof(old->DramDensity),
|
|
||||||
old->DramDensity, new->DramDensity);
|
|
||||||
fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal),
|
|
||||||
old->DramRonVal, new->DramRonVal);
|
|
||||||
fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal),
|
|
||||||
old->DramRttNomVal, new->DramRttNomVal);
|
|
||||||
fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal),
|
|
||||||
old->DramRttWrVal, new->DramRttWrVal);
|
|
||||||
fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed),
|
|
||||||
old->DramSpeed, new->DramSpeed);
|
|
||||||
fsp_display_upd_value("DramType", sizeof(old->DramType),
|
|
||||||
old->DramType, new->DramType);
|
|
||||||
fsp_display_upd_value("DramWidth", sizeof(old->DramWidth),
|
|
||||||
old->DramWidth, new->DramWidth);
|
|
||||||
fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize),
|
|
||||||
old->EccScrubBlkSize, new->EccScrubBlkSize);
|
|
||||||
fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval),
|
|
||||||
old->EccScrubInterval, new->EccScrubInterval);
|
|
||||||
fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags,
|
|
||||||
new->Flags);
|
|
||||||
fsp_display_upd_value("FspReservedMemoryLength",
|
|
||||||
sizeof(old->FspReservedMemoryLength),
|
|
||||||
old->FspReservedMemoryLength, new->FspReservedMemoryLength);
|
|
||||||
fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask,
|
|
||||||
new->RankMask);
|
|
||||||
fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress),
|
|
||||||
old->RmuBaseAddress, new->RmuBaseAddress);
|
|
||||||
fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
|
|
||||||
old->RmuLength, new->RmuLength);
|
|
||||||
fsp_display_upd_value("SerialPortBaseAddress",
|
|
||||||
sizeof(old->SerialPortBaseAddress),
|
|
||||||
old->SerialPortBaseAddress, new->SerialPortBaseAddress);
|
|
||||||
fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
|
|
||||||
old->SmmTsegSize, new->SmmTsegSize);
|
|
||||||
fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
|
|
||||||
old->SocRdOdtVal, new->SocRdOdtVal);
|
|
||||||
fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal),
|
|
||||||
old->SocWrRonVal, new->SocWrRonVal);
|
|
||||||
fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate),
|
|
||||||
old->SocWrSlewRate, new->SocWrSlewRate);
|
|
||||||
fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt,
|
|
||||||
new->SrInt);
|
|
||||||
fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp,
|
|
||||||
new->SrTemp);
|
|
||||||
fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL);
|
|
||||||
fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW);
|
|
||||||
fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS);
|
|
||||||
fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD);
|
|
||||||
fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR);
|
|
||||||
}
|
|
||||||
|
|
||||||
void soc_after_ram_init(struct romstage_params *params)
|
|
||||||
{
|
{
|
||||||
uint32_t data;
|
uint32_t data;
|
||||||
|
|
||||||
|
@ -273,7 +65,4 @@ void soc_after_ram_init(struct romstage_params *params)
|
||||||
|
|
||||||
/* Display the DRAM data */
|
/* Display the DRAM data */
|
||||||
hexdump((void *)0x000ffff0, 0x10);
|
hexdump((void *)0x000ffff0, 0x10);
|
||||||
|
|
||||||
/* Initialize the PCIe bridges */
|
|
||||||
pcie_init();
|
|
||||||
}
|
}
|
||||||
|
|
Loading…
Add table
Reference in a new issue