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UPSTREAM: soc/intel/common/block: Add LPSS function library
LPSS function library implements common register
programming under lpss.
BUG=none
BRANCH=none
TEST=none
Change-Id: If3d6662bf6502565e82a26b8def297844615e7ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 237a93c43e
Original-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19001
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/474134
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30
src/soc/intel/common/block/include/intelblocks/lpss.h
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src/soc/intel/common/block/include/intelblocks/lpss.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H
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#define SOC_INTEL_COMMON_BLOCK_LPSS_H
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#include <stdint.h>
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/* Gets controller out of reset */
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void lpss_reset_release(uintptr_t base);
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/*
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* Update clock divider parameters. Clock frequency is
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* configured as SOC_INTEL_COMMON_LPSS_CLOCK_MHZ * (M / N)
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*/
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void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
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#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */
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4
src/soc/intel/common/block/lpss/Kconfig
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src/soc/intel/common/block/lpss/Kconfig
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config SOC_INTEL_COMMON_BLOCK_LPSS
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bool
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help
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Intel Processor common LPSS support
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src/soc/intel/common/block/lpss/Makefile.inc
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src/soc/intel/common/block/lpss/Makefile.inc
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bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
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src/soc/intel/common/block/lpss/lpss.c
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src/soc/intel/common/block/lpss/lpss.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <intelblocks/lpss.h>
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/* Clock register */
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#define LPSS_CLOCK_CTL_REG 0x200
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#define LPSS_CNT_CLOCK_EN 1
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#define LPSS_CNT_CLK_UPDATE (1 << 31)
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#define LPSS_CLOCK_DIV_N(n) (((n) & 0x7fff) << 16)
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#define LPSS_CLOCK_DIV_M(m) (((m) & 0x7fff) << 1)
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/* reset register */
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#define LPSS_RESET_CTL_REG 0x204
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/*
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* Bit 1:0 controls LPSS controller reset.
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*
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* 00 ->LPSS Host Controller is in reset (Reset Asserted)
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* 01/10 ->Reserved
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* 11 ->LPSS Host Controller is NOT at reset (Reset Released)
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*/
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#define LPSS_CNT_RST_RELEASE 3
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/* DMA Software Reset Control */
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#define LPSS_DMA_RST_RELEASE (1 << 2)
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void lpss_reset_release(uintptr_t base)
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{
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uint8_t *addr = (void *)base;
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/* Take controller out of reset */
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write32(addr + LPSS_RESET_CTL_REG, LPSS_CNT_RST_RELEASE);
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}
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void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
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{
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uint8_t *addr = (void *)base;
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uint32_t clk_sel;
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addr += LPSS_CLOCK_CTL_REG;
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clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val);
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write32(addr, clk_sel | LPSS_CNT_CLK_UPDATE);
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write32(addr, clk_sel | LPSS_CNT_CLOCK_EN);
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}
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