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acer support.
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4 changed files with 123 additions and 0 deletions
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@ -17,3 +17,10 @@ void mainboard_fixup()
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host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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#endif
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#endif
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}
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}
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void final_mainboard_fixup()
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{
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void final_northbridge_fixup(void);
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final_northbridge_fixup();
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}
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109
src/northbridge/acer/m1631/chipset_init.inc
Normal file
109
src/northbridge/acer/m1631/chipset_init.inc
Normal file
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@ -0,0 +1,109 @@
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/* SPD ram init */
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#define PM_DEVFN CONFIG_ADDR(0, 0, 0)
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jmp chipsetinit_start
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/* table of settings for initial registers */
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/* format is register #, and value, OR value */
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register_table:
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.byte 0x45, 0xff, 0x14
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.byte 0x49, 0xff, 0x60
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.byte 0x50, 0xf7, 0x00
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.byte 0x52, 0xff, 0x01
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.byte 0x57, 0xff, 0x08
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.byte 0x58, 0x00, 0x40
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.byte 0x59, 0x00, 0x40
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.byte 0x61, 0x00, 0x00
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.byte 0x62, 0x00, 0x80
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.byte 0x63, 0x00, 0x08
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.byte 0x67, 0xff, 0x08
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.byte 0x6c, 0xfc, 0x00
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.byte 0x70, 0xfc, 0x00
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.byte 0x74, 0xfc, 0x00
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.byte 0x6d, 0xd7, 0x00 /* probably wrong OR value?*/
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.byte 0x71, 0xd7, 0x00 /* probably wrong OR value?*/
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.byte 0x75, 0xd7, 0x00 /* probably wrong OR value?*/
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.byte 0x6f, 0xff, 0x40
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.byte 0x73, 0xff, 0x40
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.byte 0x77, 0xff, 0x40
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.byte 0x7c, 0x00, 0x11 /* MCLK = 66 MHZ */
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.byte 0x7d, 0x00, 0xc4 /* MCLK = 66 MHZ */
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.byte 0x7e, 0x03, 0x28
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.byte 0x7f, 0xef, 0x24
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.byte 0x80, 0xf9, 0x01
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.byte 0x81, 0xb3, 0x00
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.byte 0x82, 0xff, 0x10
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.byte 0x84, 0xfe, 0x00
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.byte 0x87, 0xff, 0x00
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.byte 0x88, 0xff, 0x08
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.byte 0x8e, 0xff, 0x08
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.byte 0x93, 0xff, 0x07
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.byte 0xa0, 0x00, 0x30
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.byte 0xa1, 0x00, 0x40
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.byte 0xbc, 0x03, 0x00 /* 0 non-local video memory for now. */
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.byte 0xbd, 0xfe, 0x00 /* 0 non-local video memory for now. */
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.byte 0xc5, 0x08, 0x00 /* hardware register, set to 0 for pci skew */
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.byte 0xc8, 0x8e, 0x02
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.byte 0xc9, 0xd7, 0x07
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.byte 0xd0, 0xff, 0x00
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.byte 0xd4, 0xfd, 0x00 /* OR WITH 1 in NORTHBRIDGE_FINAL_FIXUP */
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.byte 0xd5, 0xf4, 0x10
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.byte 0xd8, 0x0f, 0x00
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.byte 0xd9, 0xff, 0x03
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.byte 0xdc, 0x00, 0x10
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.byte 0xde, 0xff, 0x04
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.byte 0xf9, 0xff, 0x4
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.byte 0xf0, 0x00, 0x50
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.byte 0xf1, 0x00, 0x04
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.byte 0xf2, 0x00, 0x09
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.byte 0xf3, 0x00, 0x1f
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.byte 0xf4, 0xff, 0x05
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.byte 0xf5, 0x00, 0x02
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.byte 0xf9, 0x00, 0x00
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.byte 0xfd, 0x00, 0x03
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.byte 0xfe, 0xff, 0x08
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.byte 0xff, 0x00, 0x03
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.byte 0x60,~0x20, 0x20
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.byte 0x02,~0xff, 0x21
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.byte 0x60,~0x20, 0x00
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.byte 0xfb,~0xff, 0x31
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.byte 0x0 /* end of table */
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chipsetinit_start:
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mov $0x3f0, %edx
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movb $0x51, %al
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outb %al, %dx
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movb $0x23, %al
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outb %al, %dx
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movb $0x2e, %al
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out %al, %dx
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movb $2, %al
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inc %edx
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outb %al, %dx
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movb $0xbb, %al
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dec %dl
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outb %al, %dx
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/* standard x86 loop on table until done code */
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/* assumes that: devfn is 0 (safe on anything we've seen) */
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/* which means addresses are a byte */
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/* address is first, then data */
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/* NOTE: read returns result in %al */
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/* WRITE expects write value in %dl, address in %al */
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movl $register_table, %esi
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1:
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xorl %edx, %edx
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xorl %eax, %eax
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movb (%esi), %cl /* save the address in %cl */
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movb %cl, %al
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testb %al, %al
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jz done_chipset_init
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PCI_READ_CONFIG_BYTE
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movb %al, %dl
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inc %esi
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andb (%esi), %dl
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inc %esi
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orb (%esi), %dl
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mov %cl, %al
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PCI_WRITE_CONFIG_BYTE
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inc %esi
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jmp 1b
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done_chipset_init:
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@ -14,3 +14,9 @@ void intel_framebuffer_on()
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{
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{
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}
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}
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#endif
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#endif
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final_northbridge_fixup()
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{
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printk("SET THAT BIT!\n");
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/* set bit 4 of north bridge register d4 to 1 */
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}
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1
src/northbridge/acer/m1631/raminit.inc
Normal file
1
src/northbridge/acer/m1631/raminit.inc
Normal file
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@ -0,0 +1 @@
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