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UPSTREAM: arch/riscv: Show fault PC and load address on load access faults

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Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/356718
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2016-06-21 19:37:03 +02:00 • committed by chrome-bot
parent 16bc916174
commit 22cd09a646
1 changed files with 2 additions and 0 deletions
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2
src/arch/riscv/trap_handler.c
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@ -122,6 +122,8 @@ void trap_handler(trapframe *tf) {
break;
case 5:
printk(BIOS_DEBUG, "Trap: Load access fault\n");
printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
printk(BIOS_DEBUG, "Load Address: %p\n", badAddr);
break;
case 6:
printk(BIOS_DEBUG, "Trap: Store address misaligned\n");