From 22cd09a6465a24f89227f7c32718118231efd2d5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Tue, 21 Jun 2016 19:37:03 +0200
Subject: [PATCH] UPSTREAM: arch/riscv: Show fault PC and load address on load
 access faults

Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/356718
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/arch/riscv/trap_handler.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index ff3be56f78..5b4d0b1801 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -122,6 +122,8 @@ void trap_handler(trapframe *tf) {
 			break;
 		case 5:
 			printk(BIOS_DEBUG, "Trap: Load access fault\n");
+			printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
+			printk(BIOS_DEBUG, "Load Address: %p\n", badAddr);
 			break;
 		case 6:
 			printk(BIOS_DEBUG, "Trap: Store address misaligned\n");