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UPSTREAM: intel/i82801gx: Reorder spaces in output

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Currently, the coreboot log of a Lenovo X60, not having any IDE devices
connected, there is a trailing whitespace in the output.

	[]
	PCI: 00:1f.1 init ...
	i82801gx_ide: initializing...
	PCI: 00:1f.1 init finished in 11 usecs
	[]

Reorder the whitespaces, so they are added when needed.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/11870
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: I640e514c89fe0246a847d1fd088def1c88e864f8
Reviewed-on: https://chromium-review.googlesource.com/414557
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Paul Menzel 2015-10-11 15:48:36 +02:00 • committed by chrome-bot
parent 2d4b491088
commit 21571328fe
1 changed files with 3 additions and 3 deletions
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6
src/southbridge/intel/i82801gx/ide.c
View file

@ -31,7 +31,7 @@ static void ide_init(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
printk(BIOS_DEBUG, "i82801gx_ide: initializing...");
if (config == NULL) {
printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
// Trying to set somewhat safe defaults instead of bailing out.
@ -57,7 +57,7 @@ static void ide_init(struct device *dev)
ideTimingConfig |= (3 << 8); // RCT = 1 clock
ideTimingConfig |= (1 << 1); // IE0
ideTimingConfig |= (1 << 0); // TIME0
printk(BIOS_DEBUG, "IDE0 ");
printk(BIOS_DEBUG, " IDE0");
}
pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
@ -71,7 +71,7 @@ static void ide_init(struct device *dev)
ideTimingConfig |= (3 << 8); // RCT = 1 clock
ideTimingConfig |= (1 << 1); // IE0
ideTimingConfig |= (1 << 0); // TIME0
printk(BIOS_DEBUG, "IDE1 ");
printk(BIOS_DEBUG, " IDE1");
}
pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);