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UPSTREAM: soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control

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This patch updates below info,
[1] Delete the DPTF_CPU_ACTIVE_AC* values because these are not
being used. Hence, removing unnecessary defines.
[2] Add new DPTF_TSR0_ACTIVE_AC* temperature trip points for TSR0
external thermal sensor. These trip points are being used by _ACx
methods to control the fan speed on Skylake-U fan based Lars and
Kunimitsu platforms.
[3] Follow up patches are using DPTF_CPU_ACTIVE_AC* temperature trip
points in board specific acpi/dptf.asl (for lars, kunimitsu, etc) to
control the fan speed as per the CPU temperature trip points.
[4] Newly added _ACx methods for thermal sensor TSR0 in this patch
has nothing to do with DPTF_CPU_ACTIVE_AC*.

We can control fan speed using various different thermal sensors.
In this patch, we have added new _ACx methods for TSR0 thermal sensor.
We run the fan at different speeds to cool down the system at different
TSR0 temperatures.

Similarly, we considered CPU sensor temperature values and ran the fan
at different speeds to cool down the system.

BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on kunimitsu and lars EVT boards.
Verified these _ACx methods with _ART table on these boards
with different workloads.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332368
Reviewed-on: https://review.coreboot.org/17067
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17
Reviewed-on: https://chromium-review.googlesource.com/408974
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Sumeet Pawnikar 2016-10-18 10:57:58 +05:30 • committed by chrome-bot
parent 733febf874
commit 175c05a41d
2 changed files with 37 additions and 20 deletions
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20
src/soc/intel/skylake/acpi/dptf/cpu.asl
View file

@ -22,26 +22,6 @@
#define DPTF_CPU_CRITICAL 90
#endif
#ifndef DPTF_CPU_ACTIVE_AC0
#define DPTF_CPU_ACTIVE_AC0 90
#endif
#ifndef DPTF_CPU_ACTIVE_AC1
#define DPTF_CPU_ACTIVE_AC1 80
#endif
#ifndef DPTF_CPU_ACTIVE_AC2
#define DPTF_CPU_ACTIVE_AC2 70
#endif
#ifndef DPTF_CPU_ACTIVE_AC3
#define DPTF_CPU_ACTIVE_AC3 60
#endif
#ifndef DPTF_CPU_ACTIVE_AC4
#define DPTF_CPU_ACTIVE_AC4 50
#endif
External (\_PR.CP00._PSS, PkgObj)
External (\_PR.CP00._TSS, PkgObj)
External (\_PR.CP00._TPC, MethodObj)

37
src/soc/intel/skylake/acpi/dptf/thermal.asl
View file

@ -110,6 +110,43 @@ Device (TSR0)
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
#ifdef DPTF_ENABLE_FAN_CONTROL
Method (_AC0)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
}
Method (_AC1)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
}
Method (_AC2)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
}
Method (_AC3)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
}
Method (_AC4)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
}
Method (_AC5)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
}
Method (_AC6)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
}
#endif
}
#endif