Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: lpss_i2c: Increase transaction timeout

Browse source 
When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.

Increase this so we can use standard speed for testing and debug in
firmware.  (as there is no way to force standard speed in the kernel)

BUG=chrome-os-partner:58666
BRANCH=None

TEST=boot eve board with cr50 TPM and I2C bus at 100khz

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17213
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Reviewed-on: https://chromium-review.googlesource.com/408973
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2016-11-03 10:43:14 -07:00 • committed by chrome-bot
parent 316f679f9d
commit 733febf874
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/soc/intel/common/lpss_i2c.c
View file

@ -73,8 +73,8 @@ struct lpss_i2c_regs {
uint32_t comp_type;
} __attribute__((packed));
/* Use a ~4ms timeout for various operations */
#define LPSS_I2C_TIMEOUT_US 4000
/* Use a ~10ms timeout for various operations */
#define LPSS_I2C_TIMEOUT_US 10000
/* High and low times in different speed modes (in ns) */
enum {