diff --git a/mainboard/pcengines/alix1c/dts b/mainboard/pcengines/alix1c/dts
index d98d5e5ba1..b3b2c968af 100644
--- a/mainboard/pcengines/alix1c/dts
+++ b/mainboard/pcengines/alix1c/dts
@@ -40,8 +40,9 @@
 		};
 		southbridge {
 			/config/("southbridge/amd/cs5536/dts");
-			pcipath = "0xf,1";
+			pcipath = "0xf,0";
 			enabled;
+			enable_ide = "1";
 		};
 		superio {
 			/config/("superio/winbond/w83627hf/dts");
diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c
index ad07780dc8..da5bad4fb3 100644
--- a/southbridge/amd/cs5536/cs5536.c
+++ b/southbridge/amd/cs5536/cs5536.c
@@ -541,6 +541,35 @@ void chipsetinit(void)
 	}
 }
 
+#define IDE_CFG	  0x40
+	#define CHANEN  (1L <<  1)
+	#define PWB	(1L << 14)
+	#define CABLE	(1L << 16)
+#define IDE_DTC	  0x48
+#define IDE_CAST  0x4C
+#define IDE_ETC	  0x50
+
+/**
+ * Enabled the IDE. This is code that is optionally run if the ide_enable is set
+ * in the mainboard dts. 
+ * 
+ * @param dev The device 
+ */
+static void ide_init(struct device *dev)
+{
+	u32 ide_cfg;
+
+	printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__);
+	/* GPIO and IRQ setup are handled in the main chipset code. */
+
+	// Enable the channel and Post Write Buffer
+	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
+	ide_cfg = pci_read_config32(dev, IDE_CFG);
+	ide_cfg |= CHANEN | PWB;
+	pci_write_config8(dev, IDE_CFG, ide_cfg);
+}
+
+
 /**
  * TODO.
  *
@@ -576,6 +605,9 @@ static void southbridge_init(struct device *dev)
 
 	enable_USB_port4(sb);
 
+	if (sb->enable_ide)
+		ide_init(dev);
+
 #warning Add back in unwanted VPCI support
 #if 0
 	/* Disable unwanted virtual PCI devices. */
@@ -588,12 +620,6 @@ static void southbridge_init(struct device *dev)
 #endif
 }
 
-static void southbridge_enable(struct device *dev)
-{
-	printk(BIOS_ERR, "cs5536: Enter %s: dev is %p\n", __FUNCTION__, dev);
-	printk(BIOS_ERR, "cs5536: Exit %s: dev is %p\n", __FUNCTION__, dev);
-}
-
 /**
  * A slightly different enable resources than the standard.
  * We grab control here as VSA has played in this chip as well.
diff --git a/southbridge/amd/cs5536/dts b/southbridge/amd/cs5536/dts
index e1c8c29971..76ffdd67ca 100644
--- a/southbridge/amd/cs5536/dts
+++ b/southbridge/amd/cs5536/dts
@@ -37,6 +37,9 @@
 	/* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */
 	enable_ide_nand_flash = "0";
 
+	/* IDE: enable CS5536 IDE. There may be a different IDE controller on board */
+	enable_ide = "0";
+
 	/* Enable USB Port 4 (0:host 1:device). */
 	enable_USBP4_device = "0";