mirror of
https://github.com/array-in-a-matrix/SAROO.git
synced 2025-04-02 10:31:43 -04:00
134 lines
2.7 KiB
Verilog
134 lines
2.7 KiB
Verilog
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///////////////////////////////////////////////////////
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// Module: Cached Bus Controller //
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///////////////////////////////////////////////////////
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module cachebus(
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reset, clk,
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cs, rd, wr, nwait, addr, wdata, rdata,
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cmd_req, cmd_ack, cache_invalid, cache_update,
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cache_addr, cache_data_1d, cache_valid
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);
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///////////////////////////////////////////////////////
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// Pins //
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///////////////////////////////////////////////////////
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// system
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input reset;
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input clk;
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// bus input
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input cs;
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input rd;
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input wr;
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output nwait;
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input[25:0] addr;
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input[15:0] wdata;
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output[15:0] rdata;
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// request output
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output[1:0] cmd_req;
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input cmd_ack;
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output cache_invalid;
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output cache_update;
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// cache interface
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input[25:3] cache_addr;
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input[63:0] cache_data_1d;
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input[ 3:0] cache_valid;
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///////////////////////////////////////////////////////
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// bus controller //
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///////////////////////////////////////////////////////
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wire[15:0] cache_data[3:0];
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assign cache_data[0] = cache_data_1d[15: 0];
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assign cache_data[1] = cache_data_1d[31:16];
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assign cache_data[2] = cache_data_1d[47:32];
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assign cache_data[3] = cache_data_1d[63:48];
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reg[ 1:0] cmd_req;
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reg cache_invalid;
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reg cache_update;
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reg[15:0] rdata;
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reg[1:0] state;
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reg nwait;
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localparam B_IDLE=0, B_WAITDATA=1, B_READ=2, B_WRITE=3;
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localparam CMD_IDLE=2'd0, CMD_WRITE=2'd1, CMD_READ=2'd2;
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always @(negedge reset or posedge clk)
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begin
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if(reset==0) begin
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state <= B_IDLE;
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nwait <= 1;
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cmd_req <= 0;
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cache_invalid <= 0;
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cache_update <= 0;
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end else begin
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case(state)
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B_IDLE: begin
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if(rd && cs) begin
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if(addr[25:3]==cache_addr) begin
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// Cache命中.
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rdata <= cache_data[addr[2:1]];
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end else begin
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// Cache未命中, 发出读请求.
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nwait <= 0;
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cmd_req <= CMD_READ;
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cache_invalid <= 1;
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state <= B_READ;
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end
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end else if(wr && cs) begin
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// 发出写请求. 如果命中Cache, 则更新数据.
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nwait <= 0;
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cmd_req <= CMD_WRITE;
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cache_update <= 1;
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state <= B_WRITE;
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end else begin
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nwait <= 1;
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cmd_req <= 0;
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cache_invalid <= 0;
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cache_update <= 0;
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end
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end
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B_READ: begin
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cache_invalid <= 0;
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if(cmd_ack) begin
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cmd_req <= 0;
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state <= B_WAITDATA;
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end
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end
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B_WAITDATA: begin
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if(cache_valid[addr[2:1]]) begin
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nwait <= 1;
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rdata <= cache_data[addr[2:1]];
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state <= B_IDLE;
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end
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end
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B_WRITE: begin
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cache_update <= 0;
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if(cmd_ack) begin
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nwait <= 1;
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cmd_req <= 0;
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state <= B_IDLE;
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end
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end
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default: begin
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state <= B_IDLE;
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end
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endcase
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end
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end
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endmodule
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