mirror of
https://github.com/array-in-a-matrix/SAROO.git
synced 2025-04-02 10:31:43 -04:00
139 lines
4.4 KiB
Tcl
139 lines
4.4 KiB
Tcl
# TCL File Generated by Component Editor 13.1
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# Mon Nov 03 17:52:21 CST 2014
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# DO NOT MODIFY
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#
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# FSMC_master "FSMC bus master" v1.0
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# tpu 2014.11.03.17:52:21
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#
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#
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#
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# request TCL package from ACDS 13.1
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#
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package require -exact qsys 13.1
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#
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# module FSMC_master
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME FSMC_master
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP Bridges/Memory-Mapped
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set_module_property AUTHOR tpu
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set_module_property DISPLAY_NAME "FSMC bus master"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL fsmc_master
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file fsmc_master.v VERILOG PATH fsmc_master.v TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point avm_clk
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#
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add_interface avm_clk clock end
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set_interface_property avm_clk clockRate 0
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set_interface_property avm_clk ENABLED true
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set_interface_property avm_clk EXPORT_OF ""
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set_interface_property avm_clk PORT_NAME_MAP ""
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set_interface_property avm_clk CMSIS_SVD_VARIABLES ""
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set_interface_property avm_clk SVD_ADDRESS_GROUP ""
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add_interface_port avm_clk avm_clk clk Input 1
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#
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# connection point avm_reset
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#
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add_interface avm_reset reset end
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set_interface_property avm_reset associatedClock avm_clk
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set_interface_property avm_reset synchronousEdges DEASSERT
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set_interface_property avm_reset ENABLED true
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set_interface_property avm_reset EXPORT_OF ""
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set_interface_property avm_reset PORT_NAME_MAP ""
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set_interface_property avm_reset CMSIS_SVD_VARIABLES ""
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set_interface_property avm_reset SVD_ADDRESS_GROUP ""
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add_interface_port avm_reset avm_reset reset Input 1
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#
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# connection point FSMC_bus
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#
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add_interface FSMC_bus conduit end
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set_interface_property FSMC_bus associatedClock ""
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set_interface_property FSMC_bus associatedReset ""
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set_interface_property FSMC_bus ENABLED true
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set_interface_property FSMC_bus EXPORT_OF ""
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set_interface_property FSMC_bus PORT_NAME_MAP ""
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set_interface_property FSMC_bus CMSIS_SVD_VARIABLES ""
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set_interface_property FSMC_bus SVD_ADDRESS_GROUP ""
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add_interface_port FSMC_bus addr export Input 32
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add_interface_port FSMC_bus ale export Input 1
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add_interface_port FSMC_bus ncs export Input 1
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add_interface_port FSMC_bus nrd export Input 1
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add_interface_port FSMC_bus nwr export Input 1
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add_interface_port FSMC_bus data_in export Input 16
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add_interface_port FSMC_bus data_out export Output 16
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add_interface_port FSMC_bus wait_out export Output 1
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#
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# connection point memory_master
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#
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add_interface memory_master avalon start
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set_interface_property memory_master addressUnits SYMBOLS
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set_interface_property memory_master associatedClock avm_clk
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set_interface_property memory_master associatedReset avm_reset
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set_interface_property memory_master bitsPerSymbol 8
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set_interface_property memory_master burstOnBurstBoundariesOnly false
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set_interface_property memory_master burstcountUnits WORDS
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set_interface_property memory_master doStreamReads false
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set_interface_property memory_master doStreamWrites false
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set_interface_property memory_master holdTime 0
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set_interface_property memory_master linewrapBursts false
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set_interface_property memory_master maximumPendingReadTransactions 0
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set_interface_property memory_master readLatency 0
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set_interface_property memory_master readWaitTime 1
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set_interface_property memory_master setupTime 0
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set_interface_property memory_master timingUnits Cycles
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set_interface_property memory_master writeWaitTime 0
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set_interface_property memory_master ENABLED true
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set_interface_property memory_master EXPORT_OF ""
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set_interface_property memory_master PORT_NAME_MAP ""
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set_interface_property memory_master CMSIS_SVD_VARIABLES ""
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set_interface_property memory_master SVD_ADDRESS_GROUP ""
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add_interface_port memory_master avm_addr address Output 32
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add_interface_port memory_master avm_rd read Output 1
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add_interface_port memory_master avm_rdvalid readdatavalid Input 1
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add_interface_port memory_master avm_rdata readdata Input 16
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add_interface_port memory_master avm_wr write Output 1
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add_interface_port memory_master avm_wdata writedata Output 16
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add_interface_port memory_master avm_wait waitrequest Input 1
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