mirror of
https://github.com/array-in-a-matrix/SAROO.git
synced 2025-04-02 10:31:43 -04:00
138 lines
4.4 KiB
Tcl
138 lines
4.4 KiB
Tcl
# TCL File Generated by Component Editor 13.1
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# Wed Nov 19 23:19:19 CST 2014
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# DO NOT MODIFY
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#
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# cdc_fifo "cdc_fifo" v1.0
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# tpu 2014.11.19.23:19:18
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# Saturn CDC FIFO
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#
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#
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# request TCL package from ACDS 13.1
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#
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package require -exact qsys 13.1
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#
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# module cdc_fifo
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#
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set_module_property DESCRIPTION "Saturn CDC FIFO"
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set_module_property NAME cdc_fifo
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Bridges and Adapters/DMA"
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set_module_property AUTHOR tpu
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set_module_property DISPLAY_NAME cdc_fifo
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL cdc_fifo
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file cdc_fifo.v VERILOG PATH cdc_fifo.v TOP_LEVEL_FILE
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add_fileset_file fifo4k.qip OTHER PATH fifo4k.qip
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add_fileset_file fifo4k.v VERILOG PATH fifo4k.v
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point conduit_end
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#
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add_interface conduit_end conduit end
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set_interface_property conduit_end associatedClock ""
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set_interface_property conduit_end associatedReset ""
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set_interface_property conduit_end ENABLED true
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set_interface_property conduit_end EXPORT_OF ""
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set_interface_property conduit_end PORT_NAME_MAP ""
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set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_end SVD_ADDRESS_GROUP ""
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add_interface_port conduit_end reg_fifo_ctrl reg_fifo_ctrl Input 16
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add_interface_port conduit_end reg_blk_addr reg_blk_addr Input 32
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add_interface_port conduit_end reg_blk_size reg_blk_size Input 16
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add_interface_port conduit_end rd_start rd_start Input 1
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add_interface_port conduit_end data_out data_out Output 16
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add_interface_port conduit_end blk_dma_end blk_dma_end Output 1
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add_interface_port conduit_end reg_fifo_stat reg_fifo_stat Output 16
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#
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# connection point read_master
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#
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add_interface read_master avalon start
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set_interface_property read_master addressUnits SYMBOLS
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set_interface_property read_master associatedClock avm_clk
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set_interface_property read_master associatedReset avm_reset
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set_interface_property read_master bitsPerSymbol 8
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set_interface_property read_master burstOnBurstBoundariesOnly false
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set_interface_property read_master burstcountUnits WORDS
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set_interface_property read_master doStreamReads false
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set_interface_property read_master doStreamWrites false
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set_interface_property read_master holdTime 0
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set_interface_property read_master linewrapBursts false
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set_interface_property read_master maximumPendingReadTransactions 0
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set_interface_property read_master readLatency 0
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set_interface_property read_master readWaitTime 1
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set_interface_property read_master setupTime 0
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set_interface_property read_master timingUnits Cycles
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set_interface_property read_master writeWaitTime 0
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set_interface_property read_master ENABLED true
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set_interface_property read_master EXPORT_OF ""
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set_interface_property read_master PORT_NAME_MAP ""
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set_interface_property read_master CMSIS_SVD_VARIABLES ""
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set_interface_property read_master SVD_ADDRESS_GROUP ""
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add_interface_port read_master avm_addr address Output 32
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add_interface_port read_master avm_rd read Output 1
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add_interface_port read_master avm_rdvalid readdatavalid Input 1
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add_interface_port read_master avm_rdata readdata Input 16
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add_interface_port read_master avm_wait waitrequest Input 1
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#
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# connection point avm_clk
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#
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add_interface avm_clk clock end
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set_interface_property avm_clk clockRate 0
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set_interface_property avm_clk ENABLED true
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set_interface_property avm_clk EXPORT_OF ""
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set_interface_property avm_clk PORT_NAME_MAP ""
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set_interface_property avm_clk CMSIS_SVD_VARIABLES ""
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set_interface_property avm_clk SVD_ADDRESS_GROUP ""
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add_interface_port avm_clk avm_clk clk Input 1
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#
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# connection point avm_reset
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#
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add_interface avm_reset reset end
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set_interface_property avm_reset associatedClock avm_clk
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set_interface_property avm_reset synchronousEdges DEASSERT
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set_interface_property avm_reset ENABLED true
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set_interface_property avm_reset EXPORT_OF ""
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set_interface_property avm_reset PORT_NAME_MAP ""
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set_interface_property avm_reset CMSIS_SVD_VARIABLES ""
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set_interface_property avm_reset SVD_ADDRESS_GROUP ""
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add_interface_port avm_reset avm_reset reset Input 1
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