mirror of
https://github.com/array-in-a-matrix/SAROO.git
synced 2025-04-02 10:31:43 -04:00
592 lines
16 KiB
Verilog
592 lines
16 KiB
Verilog
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///////////////////////////////////////////////////////
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// Module: SEGA Saturn Master Flash Card //
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///////////////////////////////////////////////////////
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// version 0.1: first step.
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module SSMaster(
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// System
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CLK_50M,
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// SDRAM
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SD_CKE, SD_CLK, SD_CS, SD_WE, SD_CAS, SD_RAS, SD_ADDR, SD_BA, SD_DQM, SD_DQ,
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// SS system
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SS_MCLK, SS_RST,
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// SS I2S output
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SS_SCLK, SS_SSEL, SS_BCK, SS_LRCK, SS_SD,
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// SS ABUS
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SS_FC0, SS_FC1, SS_TIM0, SS_TIM1, SS_TIM2, SS_AAS,
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SS_ADDR, SS_DATA, SS_CS0, SS_CS1, SS_CS2, SS_RD, SS_WR0, SS_WR1, SS_WAIT, SS_IRQ,
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SS_DATA_OE, SS_DATA_DIR,
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// STM32 FSMC
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ST_CLK, ST_AD, ST_ADDR, ST_CS, ST_RD, ST_WR, ST_BL0, ST_BL1, ST_WAIT,
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// STM32 GPIO
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ST_GPIO0, ST_GPIO1, ST_GPIO2, ST_GPIO3,
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// STM32 I2S
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ST_MCLK, ST_BCK, ST_LRCK, ST_SDO,
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// DEBUG LED
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LED0, LED1
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);
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///////////////////////////////////////////////////////
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// Pins //
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///////////////////////////////////////////////////////
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// System
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input CLK_50M;
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// SDRAM
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output SD_CKE;
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output SD_CLK;
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output SD_CS;
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output SD_WE;
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output SD_CAS;
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output SD_RAS;
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output[13:0] SD_ADDR;
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output[ 1:0] SD_BA;
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output[ 1:0] SD_DQM;
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inout[15:0] SD_DQ;
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// SS System
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input SS_MCLK;
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input SS_RST;
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// SS I2S
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input SS_SCLK;
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output SS_SSEL;
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output SS_BCK;
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output SS_LRCK;
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output SS_SD;
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// SS ABUS
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input SS_FC0;
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input SS_FC1;
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input SS_TIM0;
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input SS_TIM1;
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input SS_TIM2;
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input SS_AAS;
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input[23:0] SS_ADDR;
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inout[15:0] SS_DATA;
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input SS_CS0;
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input SS_CS1;
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input SS_CS2;
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input SS_RD;
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input SS_WR0;
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input SS_WR1;
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output SS_WAIT;
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output SS_IRQ;
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output SS_DATA_OE;
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output SS_DATA_DIR;
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// STM32 FSMC
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input ST_CLK;
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inout[15:0] ST_AD;
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input[ 7:0] ST_ADDR;
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input ST_CS;
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input ST_RD;
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input ST_WR;
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input ST_BL0;
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input ST_BL1;
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output ST_WAIT;
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// STM32 GPIO
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input ST_GPIO0;
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input ST_GPIO1;
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output ST_GPIO2;
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input ST_GPIO3;
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// STM32 I2S
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output ST_MCLK;
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input ST_BCK;
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input ST_LRCK;
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input ST_SDO;
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// DEBUG LED
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output LED0;
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output LED1;
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///////////////////////////////////////////////////////
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// Debug LED //
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///////////////////////////////////////////////////////
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assign LED0 = SS_WAIT;
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assign LED1 = ss_reg_ctrl[8];
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wire NRESET = ST_GPIO0;
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wire ST_ALE = ST_GPIO1;
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assign ST_GPIO2 = ST_IRQ;
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///////////////////////////////////////////////////////
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// I2S //
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///////////////////////////////////////////////////////
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assign ST_MCLK = SS_SCLK;
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assign SS_BCK = ST_BCK;
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assign SS_LRCK = ST_LRCK;
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assign SS_SD = ST_SDO;
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///////////////////////////////////////////////////////
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// STM32 FSMC //
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///////////////////////////////////////////////////////
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// fsmc address latch
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reg[24:0] fsmc_addr;
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reg fsmc_cs;
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always @(posedge ST_ALE)
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begin
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fsmc_addr <= {ST_ADDR, ST_AD, 1'b0};
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end
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always @(posedge ST_CS or posedge ST_ALE)
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begin
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if(ST_CS==1)
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fsmc_cs <= 1;
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else
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fsmc_cs <= 0;
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end
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// fsmc read sync
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reg stale_s0, stale_s1, stale_s2;
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always @(posedge avm_clk)
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begin
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stale_s0 <= ST_ALE;
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stale_s1 <= stale_s0;
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stale_s2 <= stale_s1;
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end
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// rising edge of ale
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wire st_rd_start = (stale_s2==0 && stale_s1==1 && ST_WR==1);
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// fsmc write sync
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reg stnwr_s0, stnwr_s1, stnwr_s2;
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always @(posedge avm_clk)
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begin
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stnwr_s0 <= ST_WR;
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stnwr_s1 <= stnwr_s0;
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stnwr_s2 <= stnwr_s1;
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end
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wire st_wr_start = (stnwr_s2==1 && stnwr_s1==0); // falling edge of wr
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///////////////////////////////////////////////////////
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// STM32 FPGA control register //
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///////////////////////////////////////////////////////
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reg[15:0] st_reg_ctrl;
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reg[15:0] ss_resp1;
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reg[15:0] ss_resp2;
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reg[15:0] ss_resp3;
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reg[15:0] ss_resp4;
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reg[31:0] st_reg_blk_addr;
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reg[15:0] st_reg_blk_size;
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reg[15:0] st_reg_fifo_ctrl;
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0) begin
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st_reg_ctrl <= 0;
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end else if(st_wr_start==1) begin
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h04) st_reg_ctrl <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h08) st_reg_blk_addr[15:0] <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h0a) st_reg_blk_addr[31:16] <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h0c) st_reg_blk_size <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h10) st_reg_fifo_ctrl <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h20) ss_resp1 <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h22) ss_resp2 <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h24) ss_resp3 <= ST_AD;
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if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h26) ss_resp4 <= ST_AD;
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end
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end
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///////////////////////////////////////////////////////
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// Saturn to STM32: HIRQ register //
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///////////////////////////////////////////////////////
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reg[15:0] ss_hirq;
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0) begin
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ss_hirq <= 0;
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end else begin
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if( st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h28)
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ss_hirq <= ss_hirq|ST_AD;
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else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h16)
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ss_hirq <= ss_hirq&(~ST_AD);
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else if(ss_wr_start==1 && ss_cdc_cs==1 && SS_ADDR[5:2]==4'b00_10)
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ss_hirq <= ss_hirq&SS_DATA;
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end
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end
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///////////////////////////////////////////////////////
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// Saturn to STM32: CDC request //
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///////////////////////////////////////////////////////
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reg st_irq_cdc;
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0) begin
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st_irq_cdc <= 1'b0;
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end else begin
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if(ss_wr_start==1 && ss_cdc_cs==1 && SS_ADDR[5:2]==4'b10_01)
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st_irq_cdc <= 1'b1;
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else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
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st_irq_cdc <= st_irq_cdc&(~ST_AD[0]);
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end
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end
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///////////////////////////////////////////////////////
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// Saturn to STM32: CMD request //
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///////////////////////////////////////////////////////
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reg st_irq_cmd;
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0) begin
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st_irq_cmd <= 1'b0;
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end else begin
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if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_110)
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st_irq_cmd <= 1'b1;
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else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
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st_irq_cmd <= st_irq_cmd&(~ST_AD[1]);
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end
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end
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///////////////////////////////////////////////////////
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// CDC FIFO dma end //
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///////////////////////////////////////////////////////
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reg st_irq_fifo;
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0) begin
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st_irq_fifo <= 1'b0;
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end else begin
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if(fifo_blk_dma_end==1)
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st_irq_fifo <= 1'b1;
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else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
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st_irq_fifo <= st_irq_fifo&(~ST_AD[2]);
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end
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end
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///////////////////////////////////////////////////////
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// Saturn to STM32: CR4 read //
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///////////////////////////////////////////////////////
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reg st_irq_cr4rd;
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0) begin
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st_irq_cr4rd <= 1'b0;
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end else begin
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if(ss_rd_start==1 && ss_cdc_cs==1 && SS_ADDR[5:2]==4'b10_01)
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st_irq_cr4rd <= 1'b1;
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else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
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st_irq_cr4rd <= st_irq_cr4rd&(~ST_AD[3]);
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end
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end
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///////////////////////////////////////////////////////
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// STM32 read data //
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///////////////////////////////////////////////////////
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reg[15:0] st_reg_data_out;
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always @(posedge avm_clk)
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begin
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st_reg_data_out <=
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(fsmc_addr[7:0]==8'h00)? 16'h5253 : // ID: "SR"
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(fsmc_addr[7:0]==8'h02)? 16'h1101 : // ver: HW1.1 && SW0.1
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(fsmc_addr[7:0]==8'h04)? st_reg_ctrl :
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(fsmc_addr[7:0]==8'h06)? st_reg_stat :
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(fsmc_addr[7:0]==8'h08)? st_reg_blk_addr[15: 0] :
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(fsmc_addr[7:0]==8'h0a)? st_reg_blk_addr[31:16] :
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(fsmc_addr[7:0]==8'h0c)? st_reg_blk_size :
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(fsmc_addr[7:0]==8'h10)? st_reg_fifo_ctrl :
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(fsmc_addr[7:0]==8'h12)? st_reg_fifo_stat :
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(fsmc_addr[7:0]==8'h14)? ss_reg_ctrl :
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(fsmc_addr[7:0]==8'h18)? ss_resp1 :
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(fsmc_addr[7:0]==8'h1a)? ss_resp2 :
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(fsmc_addr[7:0]==8'h1c)? ss_resp3 :
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(fsmc_addr[7:0]==8'h1e)? ss_resp4 :
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(fsmc_addr[7:0]==8'h20)? ss_cr1 :
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(fsmc_addr[7:0]==8'h22)? ss_cr2 :
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(fsmc_addr[7:0]==8'h24)? ss_cr3 :
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(fsmc_addr[7:0]==8'h26)? ss_cr4 :
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(fsmc_addr[7:0]==8'h28)? ss_hirq :
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(fsmc_addr[7:0]==8'h2a)? ss_hirq_mask :
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(fsmc_addr[7:0]==8'h2c)? ss_mrgb :
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(fsmc_addr[7:0]==8'h2e)? ss_reg_cmd :
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(fsmc_addr[7:0]==8'h30)? fifo_rd_times[15: 0] :
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(fsmc_addr[7:0]==8'h32)? fifo_rd_times[31:16] :
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16'hffff;
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end
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assign ST_AD = (ST_RD==0 && ST_CS==0)? (
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(fsmc_addr[24]==0)? st_reg_data_out : st_ram_data_out
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) : 16'hzzzz;
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wire st_ram_cs = !(fsmc_cs==0 && ST_ADDR[7]==1);
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wire[15:0] st_reg_stat;
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assign st_reg_stat = {pll_locked, ST_IRQ, 10'b0, st_irq_cr4rd, st_irq_fifo, st_irq_cmd, st_irq_cdc};
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wire st_irq_cr4en = st_reg_ctrl[3];
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wire st_irq_fifoen = st_reg_ctrl[2];
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wire st_irq_cmd_en = st_reg_ctrl[1];
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wire st_irq_cdc_en = st_reg_ctrl[0];
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wire ST_IRQ = ( (st_irq_cdc_en==1 && st_irq_cdc==1) ||
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(st_irq_cmd_en==1 && st_irq_cmd==1) ||
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(st_irq_cr4en ==1 && st_irq_cr4rd==1) ||
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(st_irq_fifoen==1 && st_irq_fifo==1) );
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///////////////////////////////////////////////////////
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// SATURN ABUS //
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///////////////////////////////////////////////////////
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reg sscs_s0, sscs_s1, sscs_s2, sscs_s3, sscs_s4;
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always @(posedge avm_clk)
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begin
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sscs_s0 <= (SS_CS0 & SS_CS1 & SS_CS2);
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sscs_s1 <= sscs_s0;
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sscs_s2 <= sscs_s1;
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sscs_s3 <= sscs_s2;
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sscs_s4 <= sscs_s3;
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end
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wire ss_rd_start = (sscs_s2==1 && sscs_s1==0 && SS_RD==0);
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wire ss_wr_start = (sscs_s4==1 && sscs_s3==0 && (SS_WR0==0 || SS_WR1==0));
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assign SS_DATA =(SS_RD==0 && SS_CS0==0)? ss_ram_data_out :
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(SS_RD==0 && SS_CS1==0)? ss_cs1_data_out :
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(SS_RD==0 && ss_reg_cs==1)? ss_bcr_data_out :
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(SS_RD==0 && ss_cdc_cs==1)? ss_cdc_data_out :
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16'hzzzz;
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assign SS_DATA_OE = (SS_CS0==1 && SS_CS1==1 && (SS_CS2==1 || (ss_cdc_cs==1 && SS_RD==0 && ss_cdc_en==0)));
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assign SS_DATA_DIR = (SS_WR0 & SS_WR1);
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///////////////////////////////////////////////////////
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// SATURN System Control //
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///////////////////////////////////////////////////////
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reg[15:0] ss_bcr_data_out;
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reg[15:0] ss_reg_ctrl;
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reg[15:0] ss_reg_cmd;
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reg[31:0] ss_reg_timer;
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// 00: None
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// 01: Data Cart
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// 10: RAM Cart: 1MBytes
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// 11: RAM Cart: 4MBytes
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wire[1:0] ss_cs0_type = ss_reg_ctrl[13:12];
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wire ss_reg_cs = (SS_CS2==0 && SS_ADDR[14:12]==3'b111);
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wire[15:0] ss_cs1_data_out = (SS_ADDR[23:16]==8'hff && ss_cs0_type[1]==1)?
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(
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(ss_cs0_type[0]==0)? 16'hff5a : 16'hff5c
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) : ss_ram_data_out;
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always @(posedge avm_clk)
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begin
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ss_bcr_data_out <=
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(SS_ADDR[5:1]==5'b00_000)? 16'h5253 : // ID: "SR"
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(SS_ADDR[5:1]==5'b00_001)? 16'h1101 : // ver: HW1.1 && SW0.1
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(SS_ADDR[5:1]==5'b00_010)? ss_reg_ctrl :
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(SS_ADDR[5:1]==5'b00_100)? ss_reg_timer[31:16] :
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(SS_ADDR[5:1]==5'b00_101)? ss_reg_timer[15: 0] :
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(SS_ADDR[5:1]==5'b00_110)? ss_reg_cmd :
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16'h0000;
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end
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0)
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ss_reg_ctrl <= 16'h0100;
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else if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_010)
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ss_reg_ctrl <= SS_DATA;
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end
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always @(negedge NRESET or posedge avm_clk)
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begin
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if(NRESET==0)
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ss_reg_cmd <= 4'b0000;
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else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h2e)
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ss_reg_cmd <= 0;
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else if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_110)
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ss_reg_cmd <= SS_DATA;
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end
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reg[6:0] ss_timer_feed;
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always @(posedge avm_clk)
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begin
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if(ss_timer_feed==7'd99)
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ss_timer_feed <= 0;
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else
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ss_timer_feed <= ss_timer_feed+7'b1;
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end
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always @(posedge avm_clk)
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begin
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if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_100)
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ss_reg_timer <= 0;
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else if(ss_timer_feed==0) begin
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ss_reg_timer <= ss_reg_timer+32'b1;
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end
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end
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///////////////////////////////////////////////////////
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// SATURN CDC //
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///////////////////////////////////////////////////////
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|
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reg[15:0] ss_cdc_data_out;
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reg[15:0] ss_hirq_mask;
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reg[15:0] ss_cr1;
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reg[15:0] ss_cr2;
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reg[15:0] ss_cr3;
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reg[15:0] ss_cr4;
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reg[15:0] ss_mrgb;
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|
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// enable CDC read out
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wire ss_cdc_en = ss_reg_ctrl[15];
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|
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wire ss_cdc_cs = (SS_CS2==0 && SS_ADDR[14:12]==3'b000);
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wire ss_cdc_data = (ss_cdc_cs==1 && SS_ADDR[5:2]==0);
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|
|
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always @(posedge avm_clk)
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begin
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if(ss_wr_start==1 && ss_cdc_cs==1) begin
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if(SS_ADDR[5:2]==4'b00_11) ss_hirq_mask <= SS_DATA;
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if(SS_ADDR[5:2]==4'b01_10) ss_cr1 <= SS_DATA;
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if(SS_ADDR[5:2]==4'b01_11) ss_cr2 <= SS_DATA;
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if(SS_ADDR[5:2]==4'b10_00) ss_cr3 <= SS_DATA;
|
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if(SS_ADDR[5:2]==4'b10_01) ss_cr4 <= SS_DATA;
|
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if(SS_ADDR[5:2]==4'b10_10) ss_mrgb <= SS_DATA;
|
|
end
|
|
end
|
|
|
|
always @(posedge avm_clk)
|
|
begin
|
|
ss_cdc_data_out <=
|
|
(SS_ADDR[5:2]==4'b00_00)? ss_fifo_data_out :
|
|
(SS_ADDR[5:2]==4'b00_10)? ss_hirq :
|
|
(SS_ADDR[5:2]==4'b00_11)? ss_hirq_mask :
|
|
(SS_ADDR[5:2]==4'b01_10)? ss_resp1 :
|
|
(SS_ADDR[5:2]==4'b01_11)? ss_resp2 :
|
|
(SS_ADDR[5:2]==4'b10_00)? ss_resp3 :
|
|
(SS_ADDR[5:2]==4'b10_01)? ss_resp4 :
|
|
(SS_ADDR[5:2]==4'b10_10)? ss_mrgb :
|
|
16'h0000;
|
|
end
|
|
|
|
assign SS_SSEL = ~ss_cdc_en;
|
|
|
|
assign SS_IRQ = (ss_hirq&ss_hirq_mask)==0? 1'b0: 1'b1;
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
// FIFO test
|
|
reg[31:0] fifo_rd_times;
|
|
|
|
always @(posedge avm_clk)
|
|
begin
|
|
if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h30)
|
|
fifo_rd_times <= 0;
|
|
else if(ss_rd_start==1 && ss_cdc_data==1) begin
|
|
fifo_rd_times <= fifo_rd_times+32'b1;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
///////////////////////////////////////////////////////
|
|
// QSYS //
|
|
///////////////////////////////////////////////////////
|
|
|
|
wire avm_clk;
|
|
wire pll_locked;
|
|
wire[15:0] st_ram_data_out;
|
|
|
|
wire[15:0] ss_ram_din = {SS_DATA[7:0], SS_DATA[15:8]};
|
|
wire[15:0] ss_ram_dout;
|
|
wire[15:0] ss_ram_data_out = {ss_ram_dout[7:0], ss_ram_dout[15:8]};
|
|
wire[15:0] ss_fifo_dout;
|
|
wire[15:0] ss_fifo_data_out = {ss_fifo_dout[7:0], ss_fifo_dout[15:8]};
|
|
|
|
wire[15:0] st_reg_fifo_stat;
|
|
wire fifo_blk_dma_end;
|
|
|
|
cqsys u0 (
|
|
.clk_clk (CLK_50M),
|
|
.reset_reset_n (NRESET),
|
|
.avm_clk_clk (avm_clk),
|
|
|
|
.mem_pin_addr (SD_ADDR),
|
|
.mem_pin_ba (SD_BA),
|
|
.mem_pin_cas_n (SD_CAS),
|
|
.mem_pin_cke (SD_CKE),
|
|
.mem_pin_cs_n (SD_CS),
|
|
.mem_pin_dq (SD_DQ),
|
|
.mem_pin_dqm (SD_DQM),
|
|
.mem_pin_ras_n (SD_RAS),
|
|
.mem_pin_we_n (SD_WE),
|
|
|
|
.fsmc_bus_addr ({8'b0, fsmc_addr[23:0]}),
|
|
.fsmc_bus_ncs (st_ram_cs),
|
|
.fsmc_bus_rd_start (st_rd_start),
|
|
.fsmc_bus_wr_start (st_wr_start),
|
|
.fsmc_bus_byte_en ({~ST_BL1, ~ST_BL0}),
|
|
.fsmc_bus_data_in (ST_AD),
|
|
.fsmc_bus_data_out (st_ram_data_out),
|
|
.fsmc_bus_wait_out (ST_WAIT),
|
|
|
|
.saturn_bus_addr ({7'b0, ~SS_CS1, SS_ADDR}),
|
|
.saturn_bus_ncs (SS_CS0&SS_CS1),
|
|
.saturn_bus_rd_start (ss_rd_start),
|
|
.saturn_bus_wr_start (ss_wr_start),
|
|
.saturn_bus_byte_en ({~SS_WR0, ~SS_WR1}),
|
|
.saturn_bus_data_in (ss_ram_din),
|
|
.saturn_bus_data_out (ss_ram_dout),
|
|
.saturn_bus_wait_out (SS_WAIT),
|
|
|
|
.cdc_fifo_reg_fifo_ctrl (st_reg_fifo_ctrl),
|
|
.cdc_fifo_reg_fifo_stat (st_reg_fifo_stat),
|
|
.cdc_fifo_reg_blk_addr (st_reg_blk_addr),
|
|
.cdc_fifo_reg_blk_size (st_reg_blk_size),
|
|
.cdc_fifo_rd_start ((ss_rd_start==1 && ss_cdc_data==1)),
|
|
.cdc_fifo_data_out (ss_fifo_dout),
|
|
.cdc_fifo_blk_dma_end (fifo_blk_dma_end),
|
|
|
|
.altpll_locked_export (pll_locked)
|
|
);
|
|
|
|
assign SD_CLK = avm_clk;
|
|
|
|
endmodule
|