SAROO/old/FPGA_old/SSMaster.sdc
tpu d1abb17e53 Update HW to v13(bugfix)
Change directory structs
2023-06-06 11:20:02 +08:00

10 lines
255 B
Tcl

#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks -create_base_clocks
#create_clock -name {CLOCK_50M} -period 20.000 [get_ports {CLK_50M}]