SAROO/FPGA_v12/SSMaster.sdc
2023-02-13 17:09:34 +08:00

8 lines
248 B
Tcl

#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks -create_base_clocks
create_clock -name {ST_ALE} -period 10.000 [get_ports {ST_ALE}]