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SAROO/FPGA_v12
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tpu 3d6d998c1d add put_sector_data 
reset_filter fixup
get_del_sector_data fixup
2023-04-02 22:04:43 +08:00
..
.gitignore split .gitignore file 2023-02-13 17:36:12 +08:00
cacheblk.v add v12 file 2023-02-13 17:09:34 +08:00
cachebus.v add v12 file 2023-02-13 17:09:34 +08:00
cdcfifo.qip add v12 file 2023-02-13 17:09:34 +08:00
cdcfifo.v add v12 file 2023-02-13 17:09:34 +08:00
mainpll.ppf add v12 file 2023-02-13 17:09:34 +08:00
mainpll.qip add v12 file 2023-02-13 17:09:34 +08:00
mainpll.v add v12 file 2023-02-13 17:09:34 +08:00
make_jic.tcl add v12 file 2023-02-13 17:09:34 +08:00
memhub.v add v12 file 2023-02-13 17:09:34 +08:00
readme.txt add v12 file 2023-02-13 17:09:34 +08:00
ssmaster.cdf address wrap for 1MB RAM. 2023-03-05 17:03:48 +08:00
ssmaster.cof add v12 file 2023-02-13 17:09:34 +08:00
SSMaster.qpf add v12 file 2023-02-13 17:09:34 +08:00
SSMaster.qsf add firmware update function 2023-02-28 17:28:07 +08:00
SSMaster.sdc add v12 file 2023-02-13 17:09:34 +08:00
SSMaster.v add put_sector_data 2023-04-02 22:04:43 +08:00
tsdram.v add v12 file 2023-02-13 17:09:34 +08:00

readme.txt

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V12相对于V11的改动:

1: 移除了qsys相关的组件。qsys自带的SDRAM控制器效率比较低，仅支持单次读写。
2: 实现了一个简单的SDRAM控制器，支持4次突发读。
3: 实现了一个双主端口的总线架构，每个主端口有8字节的cache。
4: 由于CDC缓存放在STM32端，现在由STM32负责填充CDC FIFO。