mirror of
https://github.com/array-in-a-matrix/SAROO.git
synced 2025-04-02 10:31:43 -04:00
137 lines
3.9 KiB
C
137 lines
3.9 KiB
C
/*
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* Sega Saturn cartridge flash tool
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* by Anders Montonen, 2012
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*
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* Original software by ExCyber
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* Graphics routines by Charles MacDonald
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*
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* Creative Commons Attribution-ShareAlike 3.0 Unported (CC BY-SA 3.0)
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*/
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#ifndef SMPC_H_
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#define SMPC_H_
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#define SMPC_BASE 0x20100000
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#define IREG0 REG8(SMPC_BASE+0x01)
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#define IREG1 REG8(SMPC_BASE+0x03)
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#define IREG2 REG8(SMPC_BASE+0x05)
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#define IREG3 REG8(SMPC_BASE+0x07)
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#define IREG4 REG8(SMPC_BASE+0x09)
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#define IREG5 REG8(SMPC_BASE+0x0b)
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#define IREG6 REG8(SMPC_BASE+0x0d)
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#define COMREG REG8(SMPC_BASE+0x1f)
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#define OREG0 REG8(SMPC_BASE+0x21)
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#define OREG1 REG8(SMPC_BASE+0x23)
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#define OREG2 REG8(SMPC_BASE+0x25)
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#define OREG3 REG8(SMPC_BASE+0x27)
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#define OREG4 REG8(SMPC_BASE+0x29)
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#define OREG5 REG8(SMPC_BASE+0x2b)
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#define OREG6 REG8(SMPC_BASE+0x2d)
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#define OREG7 REG8(SMPC_BASE+0x2f)
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#define OREG8 REG8(SMPC_BASE+0x31)
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#define OREG9 REG8(SMPC_BASE+0x33)
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#define OREG10 REG8(SMPC_BASE+0x35)
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#define OREG11 REG8(SMPC_BASE+0x37)
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#define OREG12 REG8(SMPC_BASE+0x39)
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#define OREG13 REG8(SMPC_BASE+0x3b)
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#define OREG14 REG8(SMPC_BASE+0x3d)
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#define OREG15 REG8(SMPC_BASE+0x3f)
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#define OREG16 REG8(SMPC_BASE+0x41)
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#define OREG17 REG8(SMPC_BASE+0x43)
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#define OREG18 REG8(SMPC_BASE+0x45)
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#define OREG19 REG8(SMPC_BASE+0x47)
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#define OREG20 REG8(SMPC_BASE+0x49)
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#define OREG21 REG8(SMPC_BASE+0x4b)
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#define OREG22 REG8(SMPC_BASE+0x4d)
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#define OREG23 REG8(SMPC_BASE+0x4f)
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#define OREG24 REG8(SMPC_BASE+0x51)
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#define OREG25 REG8(SMPC_BASE+0x53)
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#define OREG26 REG8(SMPC_BASE+0x55)
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#define OREG27 REG8(SMPC_BASE+0x57)
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#define OREG28 REG8(SMPC_BASE+0x59)
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#define OREG29 REG8(SMPC_BASE+0x5b)
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#define OREG30 REG8(SMPC_BASE+0x5d)
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#define OREG31 REG8(SMPC_BASE+0x5f)
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#define SR REG8(SMPC_BASE+0x61)
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#define SF REG8(SMPC_BASE+0x63)
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#define PDR1 REG8(SMPC_BASE+0x75)
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#define PDR2 REG8(SMPC_BASE+0x77)
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#define DDR1 REG8(SMPC_BASE+0x79)
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#define DDR2 REG8(SMPC_BASE+0x7b)
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#define IOSEL REG8(SMPC_BASE+0x7d)
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#define IOSEL1 1
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#define IOSEL2 2
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#define EXLE REG8(SMPC_BASE+0x7f)
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#define EXLE1 1
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#define EXLE2 2
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/* SMPC commands */
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#define MSHON 0x00
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#define SSHON 0x02
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#define SSHOFF 0x03
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#define SNDON 0x06
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#define SNDOFF 0x07
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#define CDON 0x08
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#define CDOFF 0x09
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#define SYSRES 0x0d
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#define CKCHG352 0x0e
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#define CKCHG320 0x0f
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#define INTBACK 0x10
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#define SETTIME 0x16
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#define SETSMEM 0x17
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#define NMIREQ 0x18
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#define RESENAB 0x19
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#define RESDISA 0x1a
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#define SCU_BASE 0x25FE0000
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#define ASR0 REG(SCU_BASE+0xb0)
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#define ASR1 REG(SCU_BASE+0xb4)
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#define AREF REG(SCU_BASE+0xb8)
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/* CPU SCI port */
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#define SMR REG8(0xfffffe00)
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#define BRR REG8(0xfffffe01)
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#define SCR REG8(0xfffffe02)
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#define TDR REG8(0xfffffe03)
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#define SSR REG8(0xfffffe04)
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#define RDR REG8(0xfffffe05)
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/* CPU Timer */
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#define TIER REG8(0xfffffe10)
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#define FTCSR REG8(0xfffffe11)
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#define FRCH REG8(0xfffffe12)
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#define FRCL REG8(0xfffffe13)
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#define OCRAH REG8(0xfffffe14)
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#define OCRAL REG8(0xfffffe15)
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#define OCRBH REG8(0xfffffe14)
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#define OCRBL REG8(0xfffffe15)
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#define TCR REG8(0xfffffe16)
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#define TOCR REG8(0xfffffe17)
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#define ICRH REG8(0xfffffe18)
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#define ICRL REG8(0xfffffe19)
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/* CPU UBR */
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#define BARA REG (0xffffff40)
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#define BAMRA REG (0xffffff44)
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#define BBRA REG16(0xffffff48)
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#define BARB REG (0xffffff60)
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#define BAMRB REG (0xffffff64)
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#define BBRB REG16(0xffffff68)
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#define BDRB REG (0xffffff70)
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#define BDMRB REG (0xffffff74)
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#define BRCR REG16(0xffffff78)
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#endif /* SMPC_H_ */
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