SAROO/FPGA_v11/SSMaster.sdc
2023-02-13 17:09:34 +08:00

10 lines
250 B
Tcl

#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks -create_base_clocks
create_clock -name {ST_ALE} -period 13.888 [get_ports {ST_ALE}]