mirror of
https://github.com/array-in-a-matrix/SAROO.git
synced 2025-04-02 10:31:43 -04:00
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
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#include <stm32h7xx.h>
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/******************************************************************************/
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extern uint32_t __Vectors;
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uint32_t SystemCoreClock = 400000000;
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void SystemInit (void)
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{
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/* enable CP10/CP11 (FPU) */
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SCB->CPACR = 0x00f00000;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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/* Switch to VOS1(Must enable USBREG first) */
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PWR->CR3 |= 0x03000000;
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PWR->D3CR = 0xc000;
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while((PWR->D3CR&0x2000)==0);
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/* Enable HSI48 HSE HSI */
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RCC->CR = 0x1003;
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RCC->CR |= 0x00010000;
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while((RCC->CR&0x00020000)==0);
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/* PLL config. OSC:16M DIVM=1 */
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RCC->PLLCFGR = 0x00070ccc;
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RCC->PLLCKSELR = 0x00101012;
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/* Set PLL1 VCO to 800Mhz (16x50) */
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/* P=400M Q=200M R=133M */
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RCC->PLL1DIVR = ((6-1)<<24) | ((4-1)<<16) | ((2-1)<<9) | (50-1);
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RCC->CR |= (1<<24);
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while((RCC->CR&0x02000000)==0);
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/* Set PLL2 VCO to 361.267578Mhz (16x22.5792) */
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/* P=90.316894M */
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RCC->PLL2FRACR = 0x9448;
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RCC->PLL2DIVR = ((4-1)<<9) | (22-1);
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RCC->PLLCFGR = 0x000f0cdc;
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RCC->CR |= (1<<26);
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while((RCC->CR&0x08000000)==0);
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/* CpuCLK=400M BusCLK=200M AXI=200M AHB=200M APB=100M */
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RCC->D1CFGR = 0x0048;
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RCC->D2CFGR = 0x0440;
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RCC->D3CFGR = 0x0040;
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/* per_ck=hsi_ker_ck SDMMC=PLL1_Q QSPI=AHB FMC=AHB */
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RCC->D1CCIPR = 0x00000000;
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/* SPI123=PLL2_P SPI45=APB */
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RCC->D2CCIP1R = 0x00001000;
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/* USB=HSI48 I2C=APB RNG=HSI48 USART=APB */
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RCC->D2CCIP2R = 0x00300000;
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/* All default */
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RCC->D3CCIPR = 0x00000000;
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/* RTC:1Mhz sys_ck=PLL1_P */
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RCC->CFGR = 0x2003;
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/* 4 bits for pre-emption priority, 0 bits for subpriority */
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NVIC_SetPriorityGrouping(3);
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SCB->VTOR = (uint32_t)&__Vectors;
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}
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/******************************************************************************/
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