mirror of
https://github.com/array-in-a-matrix/SAROO.git
synced 2025-04-02 10:31:43 -04:00
338 lines
6.6 KiB
C
338 lines
6.6 KiB
C
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#include "main.h"
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#include "rtx_os.h"
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#include "ff.h"
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/******************************************************************************/
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void set_mpu_entry(int index, u32 addr, u32 attr)
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{
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MPU->RNR = index;
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MPU->RBAR = addr;
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MPU->RASR = attr;
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}
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void mpu_config(void)
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{
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//set_mpu_entry(0, 0x00000000, 0x17000001|(31<<1)); // BackGround
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//set_mpu_entry(1, 0x00000000, 0x03020001|(28<<1)); // Code
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//set_mpu_entry(2, 0x20000000, 0x030b0001|(28<<1)); // SRAM
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//set_mpu_entry(3, 0x40000000, 0x13000001|(28<<1)); // InternalDevice
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set_mpu_entry(4, 0x60000000, 0x13000001|(28<<1)); // ExternalDevice
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MPU->CTRL = 0x0005;
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}
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void device_init(void)
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{
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RCC->AHB3ENR = 0x00011001; /* SDMMC1 FMC MDMA*/
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RCC->AHB1ENR = 0x08000003; /* OTG2_FS DMA2 DMA1 */
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RCC->AHB2ENR = 0xe0000000; /* SRAM3 SRAM2 SRAM1 */
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RCC->AHB4ENR = 0x000007ff; /* GPIO */
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RCC->APB1LENR = 0x0008c001; /* USART4 SPI3 SPI2 TIM2 */
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RCC->APB1HENR = 0x00000000; /* */
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RCC->APB2ENR = 0x00001001; /* SPI1 TIM1 */
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RCC->APB3ENR = 0x00000000; /* */
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RCC->APB4ENR = 0x00010002; /* RTC SYSCFG */
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RCC->AHB1LPENR &= ~0x14000000;
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GPIOA->MODER = 0x2aa00000;
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GPIOA->OTYPER = 0x00000018;
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GPIOA->OSPEEDR= 0x16805400;
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GPIOA->PUPDR = 0x40000040;
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GPIOA->AFR[0] = 0x55500000;
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GPIOA->AFR[1] = 0x000aaa00;
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GPIOA->ODR = 0x00000008;
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GPIOB->MODER = 0x8a0a9a80;
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GPIOB->OTYPER = 0x00000000;
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GPIOB->OSPEEDR= 0x8a008a80;
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GPIOB->PUPDR = 0x00400008;
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GPIOB->AFR[0] = 0xc0766000;
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GPIOB->AFR[1] = 0x55550088;
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GPIOB->ODR = 0x00000040;
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GPIOC->MODER = 0x06aa2400;
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GPIOC->OTYPER = 0x00000000;
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GPIOC->OSPEEDR= 0x02aa2000;
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GPIOC->PUPDR = 0x00000100;
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GPIOC->AFR[0] = 0x05000000;
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GPIOC->AFR[1] = 0x000ccccc;
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GPIOD->MODER = 0xaaaaaaaa;
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GPIOD->OTYPER = 0x00000000;
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GPIOD->OSPEEDR= 0xaaaaaaaa;
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GPIOD->PUPDR = 0x00000000;
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GPIOD->AFR[0] = 0xcccccccc;
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GPIOD->AFR[1] = 0xcccccccc;
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GPIOE->MODER = 0xaaaaaaaa;
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GPIOE->OTYPER = 0x00000000;
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GPIOE->OSPEEDR= 0xaaaaaaaa;
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GPIOE->PUPDR = 0x00000000;
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GPIOE->AFR[0] = 0xcccccccc;
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GPIOE->AFR[1] = 0xcccccccc;
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uart4_init();
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// FMC<4D>ĵ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ģʽ, ֻ<><D6BB>MTypeΪPSRAM/FLASHʱ<48><CAB1><EFBFBD><EFBFBD>.
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// <20><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>: ExtMode > MuxMode > Mode1/2
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// PSRAMģʽ<C4A3><CABD>, <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>չΪ<D5B9><CEAA>BL<42>źŵ<C5BA>4<EFBFBD><34>д<EFBFBD><D0B4>. <20><><EFBFBD><EFBFBD>FMCֻ<43><D6BB>ѡ<EFBFBD><D1A1>FLASHģʽ.
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// FMC_CS1: 0xc0000000
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FMC_Bank1_R->BTCR[0] = 0x8000b05b;
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FMC_Bank1_R->BTCR[1] = 0x00020612;
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}
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/******************************************************************************/
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void do_hardfault(u32 *sp, u32 *esp)
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{
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char hbuf[128];
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int i;
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for(i=0; i<10000000; i++){
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__asm volatile("nop");
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}
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_puts("\r\n\r\nHardFault!\r\n");
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sprintk(hbuf, "HFSR=%08x CFSR=%08x BFAR=%08x MMFAR=%08x\n",
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SCB->HFSR, SCB->CFSR, SCB->BFAR, SCB->MMFAR);
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_puts(hbuf);
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sprintk(hbuf, " R0 : %08x\n", esp[0]); _puts(hbuf);
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sprintk(hbuf, " R1 : %08x\n", esp[1]); _puts(hbuf);
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sprintk(hbuf, " R2 : %08x\n", esp[2]); _puts(hbuf);
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sprintk(hbuf, " R3 : %08x\n", esp[3]); _puts(hbuf);
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sprintk(hbuf, " R4 : %08x\n", sp[0]); _puts(hbuf);
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sprintk(hbuf, " R5 : %08x\n", sp[1]); _puts(hbuf);
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sprintk(hbuf, " R6 : %08x\n", sp[2]); _puts(hbuf);
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sprintk(hbuf, " R7 : %08x\n", sp[3]); _puts(hbuf);
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sprintk(hbuf, " R8 : %08x\n", sp[4]); _puts(hbuf);
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sprintk(hbuf, " R9 : %08x\n", sp[5]); _puts(hbuf);
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sprintk(hbuf, " R10: %08x\n", sp[6]); _puts(hbuf);
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sprintk(hbuf, " R11: %08x\n", sp[7]); _puts(hbuf);
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sprintk(hbuf, " R12: %08x\n", esp[4]); _puts(hbuf);
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sprintk(hbuf, " SP : %08x\n", esp); _puts(hbuf);
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sprintk(hbuf, " LR : %08x\n", esp[5]); _puts(hbuf);
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sprintk(hbuf, " PC : %08x\n", esp[6]); _puts(hbuf);
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sprintk(hbuf, " PSR: %08x\n", esp[7]); _puts(hbuf);
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while(1);
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}
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/******************************************************************************/
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void *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type);
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uint32_t osRtxMemoryFree (void *mem, void *block);
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void *malloc(uint32_t size)
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{
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void *p = osRtxMemoryAlloc(osRtxInfo.mem.common, size, 0);
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//printk("malloc: %08x %d\n", p, size);
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return p;
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}
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void free(void *p)
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{
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//printk("free: %08x\n", p);
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osRtxMemoryFree(osRtxInfo.mem.common, p);
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}
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void memcpy32(void *dst, void *src, int len)
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{
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u32 *dp = (u32*)dst;
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u32 *sp = (u32*)src;
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while(len>0){
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*dp++ = *sp++;
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len -= 4;
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}
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}
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/******************************************************************************/
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int flash_erase(int addr)
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{
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int retv;
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if(FLASH->CR1 & 1){
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FLASH->KEYR1 = 0x45670123;
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FLASH->KEYR1 = 0xcdef89ab;
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}
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addr = (addr>>17)&7;
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FLASH->CR1 = 0x0024 | (addr<<8);
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FLASH->CR1 = 0x00a4 | (addr<<8);
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while(FLASH->SR1&7);
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retv = FLASH->SR1 & 0x07fe0000;
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FLASH->CCR1 = FLASH->SR1;
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FLASH->CR1 = 0x0000;
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return retv;
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}
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int flash_write32(int addr, u8 *buf)
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{
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int i, retv;
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if(FLASH->CR1 & 1){
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FLASH->KEYR1 = 0x45670123;
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FLASH->KEYR1 = 0xcdef89ab;
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}
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FLASH->CR1 = 0x0022;
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__DSB();
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for(i=0; i<32; i+=4){
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*(volatile u32*)(addr+i) = *(u32*)(buf+i);
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}
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__DSB();
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while(FLASH->SR1&7);
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retv = FLASH->SR1 & 0x07fe0000;
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FLASH->CCR1 = FLASH->SR1;
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FLASH->CR1 = 0x0000;
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return retv;
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}
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int flash_update(int check)
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{
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FIL fp;
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int i, addr, retv, fsize;
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u8 *fbuf = (u8*)0x24002000;
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// <20><><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>.
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retv = f_open(&fp, "/SAROO/update/ssmaster.bin", FA_READ);
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if(retv){
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printk("No firm file.\n");
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return -1;
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}
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fsize = f_size(&fp);
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printk("Found firm file.\n");
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printk(" Size %08x\n", fsize);
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if(check){
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f_close(&fp);
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return 0;
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}
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u32 rv;
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f_read(&fp, fbuf, fsize, &rv);
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disable_irq();
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int firm_addr = 0x08000000;
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_puts("erase ...\n");
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retv = flash_erase(firm_addr);
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if(retv){
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_puts(" faile!\n");
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f_close(&fp);
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return -2;
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}
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_puts("write ...\n");
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for(i=0; i<fsize; i+=32){
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retv = flash_write32(firm_addr+i, fbuf+i);
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if(retv){
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_puts(" faile!\n");
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f_close(&fp);
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return -3;
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}
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}
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f_close(&fp);
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_puts("done.\n");
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return 0;
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}
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/******************************************************************************/
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FATFS sdfs;
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void fs_mount(void *arg)
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{
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FRESULT retv;
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retv = f_mount(&sdfs, "0:", 1);
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printk("Mount SDFS: %08x\n\n", retv);
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if(retv==0){
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//scan_dir("/", 0, NULL);
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}
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}
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/******************************************************************************/
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void fpga_config(void);
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void main_task(void *arg)
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{
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int cnt = 0;
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device_init();
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printk("\n\nSSMaster start! %s %s\n\n", __DATE__, __TIME__);
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mpu_config();
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sdio_init();
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fs_mount(0);
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fpga_config();
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saturn_config();
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simple_shell();
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while(1){
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GPIOC->BSRR = 0x2000<<16;
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osDelay(50);
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GPIOC->BSRR = 0x2000;
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osDelay(50);
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cnt += 1;
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}
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}
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int main(void)
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{
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osKernelInitialize();
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osThreadAttr_t attr;
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memset(&attr, 0, sizeof(attr));
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attr.priority = osPriorityLow;
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osThreadNew(main_task, NULL, &attr);
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osKernelStart();
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return 0;
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}
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