SAROO/FPGA_v12/readme.txt
2023-02-13 17:09:34 +08:00

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V12相对于V11的改动:
1: 移除了qsys相关的组件。qsys自带的SDRAM控制器效率比较低仅支持单次读写。
2: 实现了一个简单的SDRAM控制器支持4次突发读。
3: 实现了一个双主端口的总线架构每个主端口有8字节的cache。
4: 由于CDC缓存放在STM32端现在由STM32负责填充CDC FIFO。