/* Quartus II 64-Bit Version 14.1.1 Build 190 01/19/2015 SJ Full Version */
JedecChain;
	FileRevision(JESD32A);
	DefaultMfr(6E);

	P ActionCode(Cfg)
		Device PartName(EP4CE6) Path("D:/project/SAROO/FPGA_v12/output_files/") File("ssmaster.jic") MfrSpec(OpMask(1) SEC_Device(EPCS16) Child_OpMask(1 3));

ChainEnd;

AlteraBegin;
	ChainType(JTAG);
AlteraEnd;