From 13f15e041edab3999fa17d51b0b31a70f676148d Mon Sep 17 00:00:00 2001
From: tpu <tpunix@126.com>
Date: Sun, 5 Mar 2023 17:03:48 +0800
Subject: [PATCH] address wrap for 1MB RAM.

---
 FPGA_v12/SSMaster.v   | 16 +++++++++++++++-
 FPGA_v12/ssmaster.cdf |  2 +-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/FPGA_v12/SSMaster.v b/FPGA_v12/SSMaster.v
index d5dd8fe..2dfbc92 100644
--- a/FPGA_v12/SSMaster.v
+++ b/FPGA_v12/SSMaster.v
@@ -649,7 +649,7 @@ module SSMaster(
 	// 03000000 - 04000000 : 16MB Free Space
 	// Saturn is BigEndian system
 	wire ss_ram_cs = ~SS_CS0;
-	wire[25:0] ss_ram_addr = {2'b0, SS_ADDR};
+	//wire[25:0] ss_ram_addr = {2'b0, SS_ADDR};
 	wire[ 1:0] ss_mask = {SS_WR0,SS_WR1};
 	wire[15:0] ss_ram_din = {SS_DATA[7:0], SS_DATA[15:8]};
 	wire[15:0] ss_ram_dout;
@@ -657,6 +657,20 @@ module SSMaster(
 	wire ss_ram_wait;
 
 
+	reg[25:0] ss_ram_addr;
+	always @(posedge mclk)
+	begin
+		ss_ram_addr[25:24] <= 2'b0;
+		ss_ram_addr[23:21] <= SS_ADDR[23:21];
+
+		if(SS_ADDR[23:22]==2'b01 && ss_cs0_type==2'b10)
+			ss_ram_addr[20:19] <= 2'b00;
+		else
+			ss_ram_addr[20:19] <= SS_ADDR[20:19];
+
+		ss_ram_addr[18: 0] <= SS_ADDR[18:0];
+	end
+
 	memhub _mh(
 		NRESET, mclk,
 		ss_ram_cs, ss_rd_start, ss_wr_start, ss_mask, ss_ram_wait, ss_ram_addr, ss_ram_din, ss_ram_dout,
diff --git a/FPGA_v12/ssmaster.cdf b/FPGA_v12/ssmaster.cdf
index fb9cd98..16606e9 100644
--- a/FPGA_v12/ssmaster.cdf
+++ b/FPGA_v12/ssmaster.cdf
@@ -4,7 +4,7 @@ JedecChain;
 	DefaultMfr(6E);
 
 	P ActionCode(Cfg)
-		Device PartName(EP4CE6) Path("D:/project/SAROO_work/FPGA_v12/output_files/") File("ssmaster.jic") MfrSpec(OpMask(1) SEC_Device(EPCS16) Child_OpMask(1 3));
+		Device PartName(EP4CE6) Path("D:/project/SAROO/FPGA_v12/output_files/") File("ssmaster.jic") MfrSpec(OpMask(1) SEC_Device(EPCS16) Child_OpMask(1 3));
 
 ChainEnd;