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https://github.com/xqemu/xqemu.git
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c230d77bc2
Cromwell sets these registers on video initialization and guest OS should be able to read them in order to obtain current screen resolution set up by firmware.
135 lines
4 KiB
C
135 lines
4 KiB
C
/*
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* QEMU Geforce NV2A implementation
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*
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* Copyright (c) 2012 espes
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* Copyright (c) 2015 Jannik Vogel
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* Copyright (c) 2018 Matt Borgerson
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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uint64_t pramdac_read(void *opaque, hwaddr addr, unsigned int size)
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{
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NV2AState *d = (NV2AState *)opaque;
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uint64_t r = 0;
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switch (addr & ~3) {
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case NV_PRAMDAC_NVPLL_COEFF:
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r = d->pramdac.core_clock_coeff;
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break;
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case NV_PRAMDAC_MPLL_COEFF:
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r = d->pramdac.memory_clock_coeff;
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break;
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case NV_PRAMDAC_VPLL_COEFF:
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r = d->pramdac.video_clock_coeff;
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break;
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case NV_PRAMDAC_PLL_TEST_COUNTER:
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/* emulated PLLs locked instantly? */
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r = NV_PRAMDAC_PLL_TEST_COUNTER_VPLL2_LOCK
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| NV_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK
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| NV_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK
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| NV_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK;
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break;
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case NV_PRAMDAC_GENERAL_CONTROL:
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r = d->pramdac.general_control;
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break;
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case NV_PRAMDAC_FP_VDISPLAY_END:
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r = d->pramdac.fp_vdisplay_end;
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break;
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case NV_PRAMDAC_FP_VCRTC:
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r = d->pramdac.fp_vcrtc;
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break;
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case NV_PRAMDAC_FP_VSYNC_END:
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r = d->pramdac.fp_vsync_end;
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break;
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case NV_PRAMDAC_FP_VVALID_END:
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r = d->pramdac.fp_vvalid_end;
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break;
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case NV_PRAMDAC_FP_HDISPLAY_END:
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r = d->pramdac.fp_hdisplay_end;
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break;
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case NV_PRAMDAC_FP_HCRTC:
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r = d->pramdac.fp_hcrtc;
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break;
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case NV_PRAMDAC_FP_HVALID_END:
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r = d->pramdac.fp_hvalid_end;
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break;
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default:
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break;
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}
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/* Surprisingly, QEMU doesn't handle unaligned access for you properly */
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r >>= 32 - 8 * size - 8 * (addr & 3);
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NV2A_DPRINTF("PRAMDAC: read %d [0x%" HWADDR_PRIx "] -> %llx\n", size, addr, r);
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return r;
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}
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void pramdac_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
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{
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NV2AState *d = (NV2AState *)opaque;
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uint32_t m, n, p;
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reg_log_write(NV_PRAMDAC, addr, val);
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switch (addr) {
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case NV_PRAMDAC_NVPLL_COEFF:
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d->pramdac.core_clock_coeff = val;
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m = val & NV_PRAMDAC_NVPLL_COEFF_MDIV;
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n = (val & NV_PRAMDAC_NVPLL_COEFF_NDIV) >> 8;
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p = (val & NV_PRAMDAC_NVPLL_COEFF_PDIV) >> 16;
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if (m == 0) {
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d->pramdac.core_clock_freq = 0;
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} else {
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d->pramdac.core_clock_freq = (NV2A_CRYSTAL_FREQ * n)
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/ (1 << p) / m;
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}
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break;
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case NV_PRAMDAC_MPLL_COEFF:
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d->pramdac.memory_clock_coeff = val;
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break;
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case NV_PRAMDAC_VPLL_COEFF:
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d->pramdac.video_clock_coeff = val;
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break;
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case NV_PRAMDAC_GENERAL_CONTROL:
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d->pramdac.general_control = val;
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break;
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case NV_PRAMDAC_FP_VDISPLAY_END:
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d->pramdac.fp_vdisplay_end = val;
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break;
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case NV_PRAMDAC_FP_VCRTC:
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d->pramdac.fp_vcrtc = val;
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break;
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case NV_PRAMDAC_FP_VSYNC_END:
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d->pramdac.fp_vsync_end = val;
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break;
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case NV_PRAMDAC_FP_VVALID_END:
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d->pramdac.fp_vvalid_end = val;
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break;
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case NV_PRAMDAC_FP_HDISPLAY_END:
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d->pramdac.fp_hdisplay_end = val;
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break;
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case NV_PRAMDAC_FP_HCRTC:
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d->pramdac.fp_hcrtc = val;
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break;
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case NV_PRAMDAC_FP_HVALID_END:
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d->pramdac.fp_hvalid_end = val;
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break;
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default:
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break;
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}
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}
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