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89ece6f76f
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_e_prci model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20 lines
1.1 KiB
Meson
20 lines
1.1 KiB
Meson
riscv_ss = ss.source_set()
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riscv_ss.add(files('boot.c'), fdt)
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riscv_ss.add(files('numa.c'))
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riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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hw_arch += {'riscv': riscv_ss}
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