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41195d236e
ARC common code to enable a SMP system + ISS provided SMP extensions. ARC700 natively lacks SMP support, hence some of the core features are are only enabled if SoCs have the necessary h/w pixie-dust. This includes: -Inter Processor Interrupts (IPI) -Cache coherency -load-locked/store-conditional ... The low level exception handling would be completely broken in SMP because we don't have hardware assisted stack switching. Thus a fair bit of this code is repurposing the MMU_SCRATCH reg for event handler prologues to keep them re-entrant. Many thanks to Rajeshwar Ranga for his initial "major" contributions to SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help with resurrecting that in 3.2 kernel (2012). Note that this platform code is again singleton design pattern - so multiple SMP platforms won't build at the moment - this deficiency is addressed in subsequent patches within this series. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rajeshwar Ranga <rajeshwar.ranga@gmail.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Gilad Ben-Yossef <gilad@benyossef.com>
35 lines
668 B
C
35 lines
668 B
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Feb 2009
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* -For AA4 board, IRQ assignments to peripherals
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*/
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#ifndef __PLAT_IRQ_H
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#define __PLAT_IRQ_H
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#ifdef CONFIG_SMP
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#define NR_IRQS 32
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#else
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#define NR_IRQS 16
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#endif
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#define UART0_IRQ 5
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#define UART1_IRQ 10
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#define UART2_IRQ 11
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#define VMAC_IRQ 6
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#define IDE_IRQ 13
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#define PCI_IRQ 14
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#define PS2_IRQ 15
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#ifdef CONFIG_SMP
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#define IDU_INTERRUPT_0 16
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#endif
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#endif
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