Emulation/switch-linux
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-linux.git synced 2025-05-04 02:34:21 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'drm-fixes-4.13' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Browse source 
Just a few small fixes for 4.13.

* 'drm-fixes-4.13' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu: Use list_del_init in amdgpu_mn_unregister
  drm/amdgpu: Fix undue fallthroughs in golden registers initialization
  drm/amdgpu: fix header on gfx9 clear state
This commit is contained in:
Dave Airlie 2017-08-04 11:43:14 +10:00
commit 5669b9989e
3 changed files with 24 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
View file

@ -359,7 +359,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
head = bo->mn_list.next; head = bo->mn_list.next;
bo->mn = NULL; bo->mn = NULL;
list_del(&bo->mn_list); list_del_init(&bo->mn_list);
if (list_empty(head)) { if (list_empty(head)) {
struct amdgpu_mn_node *node; struct amdgpu_mn_node *node;

41
drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
View file

@ -1,24 +1,25 @@
/* /*
*************************************************************************************************** * Copyright 2017 Advanced Micro Devices, Inc.
* *
* Trade secret of Advanced Micro Devices, Inc. * Permission is hereby granted, free of charge, to any person obtaining a
* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished) * copy of this software and associated documentation files (the "Software"),
* * to deal in the Software without restriction, including without limitation
* All rights reserved. This notice is intended as a precaution against inadvertent publication and * the rights to use, copy, modify, merge, publish, distribute, sublicense,
* does not imply publication or any waiver of confidentiality. The year included in the foregoing * and/or sell copies of the Software, and to permit persons to whom the
* notice is the year of creation of the work. * Software is furnished to do so, subject to the following conditions:
* *
*************************************************************************************************** * The above copyright notice and this permission notice shall be included in
*/ * all copies or substantial portions of the Software.
/** *
*************************************************************************************************** * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* @brief gfx9 Clearstate Definitions * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*************************************************************************************************** * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* Do not edit! This is a machine-generated file! * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
*/ * OTHER DEALINGS IN THE SOFTWARE.
*
*/
static const unsigned int gfx9_SECT_CONTEXT_def_1[] = static const unsigned int gfx9_SECT_CONTEXT_def_1[] =
{ {

2
drivers/gpu/drm/amd/amdgpu/si.c
View file

@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
pitcairn_mgcg_cgcg_init, pitcairn_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
break;
case CHIP_VERDE: case CHIP_VERDE:
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
verde_golden_registers, verde_golden_registers,
@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
oland_mgcg_cgcg_init, oland_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
break;
case CHIP_HAINAN: case CHIP_HAINAN:
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
hainan_golden_registers, hainan_golden_registers,