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hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs

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The max junction temperature of Atom N450/D410/D510 CPUs is 100 degrees
Celsius. Since these CPUs are always coupled with Intel NM10 chipset in
one package, the best way to verify whether an Atom CPU is N450/D410/D510
is to check the host bridge device.

Signed-off-by: Yong Wang <yong.y.wang@intel.com>
Acked-by: Huaxu Wan <huaxu.wan@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
This commit is contained in:
Yong Wang 2010-01-10 20:52:34 +01:00 • committed by Jean Delvare
parent c5114a1cd6
commit 1fe63ab47a
2 changed files with 15 additions and 3 deletions
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2
drivers/hwmon/Kconfig
View file

@ -392,7 +392,7 @@ config SENSORS_GL520SM
config SENSORS_CORETEMP config SENSORS_CORETEMP
tristate "Intel Core/Core2/Atom temperature sensor" tristate "Intel Core/Core2/Atom temperature sensor"
depends on X86 && EXPERIMENTAL depends on X86 && PCI && EXPERIMENTAL
help help
If you say yes here you get support for the temperature If you say yes here you get support for the temperature
sensor inside your CPU. Most of the family 6 CPUs sensor inside your CPU. Most of the family 6 CPUs

16
drivers/hwmon/coretemp.c
View file

@ -33,6 +33,7 @@
#include <linux/list.h> #include <linux/list.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/cpu.h> #include <linux/cpu.h>
#include <linux/pci.h>
#include <asm/msr.h> #include <asm/msr.h>
#include <asm/processor.h> #include <asm/processor.h>
@ -161,6 +162,7 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
int usemsr_ee = 1; int usemsr_ee = 1;
int err; int err;
u32 eax, edx; u32 eax, edx;
struct pci_dev *host_bridge;
/* Early chips have no MSR for TjMax */ /* Early chips have no MSR for TjMax */
@ -168,11 +170,21 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
usemsr_ee = 0; usemsr_ee = 0;
} }
/* Atoms seems to have TjMax at 90C */ /* Atom CPUs */
if (c->x86_model == 0x1c) { if (c->x86_model == 0x1c) {
usemsr_ee = 0; usemsr_ee = 0;
tjmax = 90000;
host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
&& (host_bridge->device == 0xa000 /* NM10 based nettop */
|| host_bridge->device == 0xa010)) /* NM10 based netbook */
tjmax = 100000;
else
tjmax = 90000;
pci_dev_put(host_bridge);
} }
if ((c->x86_model > 0xe) && (usemsr_ee)) { if ((c->x86_model > 0xe) && (usemsr_ee)) {