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240 commits 12 branches 1 tag 797 KiB
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Author SHA1 Message Date
Lionel Flandrin
5da2eabe96 Implement 16bit load from RAM 2015-05-25 16:26:14 +02:00
Lionel Flandrin
c71e6687d2 Implement LHU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
1e97374db6 Ignore read and writes from/to DMA 2015-05-25 16:26:14 +02:00
Lionel Flandrin
048981061d Implement RAM 16bit store 2015-05-25 16:26:14 +02:00
Lionel Flandrin
5428383153 Trigger an exception when the PC is not correctly aligned 2015-05-25 16:26:14 +02:00
Lionel Flandrin
e993ec9307 Generate exception on unaligned load/store 2015-05-25 16:26:14 +02:00
Lionel Flandrin
58e3216b74 Add overflow exception to ADD and ADDI 2015-05-25 16:26:14 +02:00
Lionel Flandrin
796794c46d Implement exceptions from branch delay slots 2015-05-25 16:26:14 +02:00
Lionel Flandrin
18e8224a5c Implement RFE 2015-05-25 16:26:14 +02:00
Lionel Flandrin
0ab609c686 Implement MTHI and MTLO 2015-05-25 16:26:14 +02:00
Lionel Flandrin
0861f9df0d Change branch delay slot handling (next_instruction -> next_pc) 2015-05-25 16:26:14 +02:00
Lionel Flandrin
dda052657b Placeholder code for IRQ control reads and timer writes 2015-05-25 16:26:14 +02:00
Lionel Flandrin
657a9fe81f Implement MFHI and SLT 2015-05-25 16:26:14 +02:00
Lionel Flandrin
f832644a56 Implement DIVU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
027a008a9d Implement SLTIU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
42dc14a81f Implement SRL 2015-05-25 16:26:14 +02:00
Lionel Flandrin
66993dfa10 Implement MFLO 2015-05-25 16:26:14 +02:00
Lionel Flandrin
f145ac874d Implement DIV 2015-05-25 16:26:14 +02:00
Lionel Flandrin
2b20d4593f Implement SRA 2015-05-25 16:26:14 +02:00
Lionel Flandrin
75f4ec2ff1 Implement SUBU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
67269dc7f3 Implement SLTI 2015-05-25 16:26:14 +02:00
Lionel Flandrin
60163c4b0a Implement BGEZ, BLTZ, BGEZAL, BLTZAL 2015-05-25 16:26:14 +02:00
Lionel Flandrin
a4a4a29b22 Implement JALR 2015-05-25 16:26:14 +02:00
Lionel Flandrin
07ec507b3c Implement LBU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
9172f04543 Implement BLEZ 2015-05-25 16:26:14 +02:00
Lionel Flandrin
fb9f92fe3c Implement BGTZ 2015-05-25 16:26:14 +02:00
Lionel Flandrin
231b2452e2 Implement IRQ control regs 2015-05-25 16:26:14 +02:00
Lionel Flandrin
01d27a1f54 Implement ADD 2015-05-25 16:26:14 +02:00
Lionel Flandrin
b701d9e2e6 Implement MFC0 and AND 2015-05-25 16:26:14 +02:00
Lionel Flandrin
044ce85ad2 Implement RAM load8/store8 2015-05-25 16:26:14 +02:00
Lionel Flandrin
ac0fcd3b80 Implement LB, BEQ 2015-05-25 16:26:13 +02:00
Lionel Flandrin
366c0edcde Implement SB and JR 2015-05-25 16:25:39 +02:00
Lionel Flandrin
f374ae82ae Implement JAL 2015-05-25 16:25:39 +02:00
Lionel Flandrin
049843eca7 Handle regions 2015-05-25 16:25:38 +02:00
Lionel Flandrin
9d761378bb Implement ADDU and SLTU 2015-05-25 16:24:54 +02:00
Lionel Flandrin
62a25a6693 Implement load delay slot and RAM 2015-05-25 16:24:53 +02:00
Lionel Flandrin
fa1b031dc5 Implemented BNE and ADDI 2015-05-25 16:24:31 +02:00
Lionel Flandrin
05043a36c3 Implement MTC0 2015-05-25 16:24:31 +02:00
Lionel Flandrin
21aa073e79 Ignore writes to CACHE_CONTROL for now 2015-05-25 16:24:29 +02:00
Lionel Flandrin
017db106ea First instructions: LUI and ORI 2015-05-25 16:23:57 +02:00