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Author SHA1 Message Date
Lionel Flandrin
519f11c40f Implement GP1(0x03): Display Enable 2015-05-25 16:26:15 +02:00
Lionel Flandrin
de1e0ee3e8 Implement GP0(0xA0): Image Load 2015-05-25 16:26:15 +02:00
Lionel Flandrin
5483ab4853 Ignore GP0(0x01) Clear Cache command 2015-05-25 16:26:15 +02:00
Lionel Flandrin
002b441049 Implement temporary hack to avoid BIOS lockup. 
At the moment if the vertical resolution is set to 480 lines (bit 19
of GPUSTAT is set) the BIOS deadlocks waiting for bit `31` of the same
GPUSTAT register to flip. To avoid this I lie and pretend the vertical
resolution is always 240 lines.
 2015-05-25 16:26:15 +02:00
Lionel Flandrin
caa99b608f Implemented placeholder for GP0(0x28): gp0_quad_mono_opaque 2015-05-25 16:26:15 +02:00
Lionel Flandrin
08465448ca GPU GP0: Add support for multi-word commands 2015-05-25 16:26:15 +02:00
Lionel Flandrin
4cfa4efee9 Implement GPU GP1: Display Horizontal and Vertical Range 2015-05-25 16:26:15 +02:00
Lionel Flandrin
72d8fbce12 Implement GPU GP1: Display VRAM Start 2015-05-25 16:26:15 +02:00
Lionel Flandrin
3626b50811 Implement GPU GP0: Mask Bit Setting 2015-05-25 16:26:15 +02:00
Lionel Flandrin
9cc7e49727 Implement GPU GP0: Texture Window 2015-05-25 16:26:15 +02:00
Lionel Flandrin
502fec2f86 Implement GPU GP0: Set Drawing Offset 2015-05-25 16:26:15 +02:00
Lionel Flandrin
61b46bd5da Fix comments: retreive -> retrieve 2015-05-25 16:26:15 +02:00
Lionel Flandrin
74103f9336 Implement GPU GP0: See Drawing Area 2015-05-25 16:26:15 +02:00
Lionel Flandrin
c0396609fe Implemented GPU GP1: DMA Direction 2015-05-25 16:26:15 +02:00
Lionel Flandrin
75e5ac572a Implement GPU GP1: Display Mode 2015-05-25 16:26:15 +02:00
Lionel Flandrin
5c243be66f Implement placeholder GPUREAD register 2015-05-25 16:26:15 +02:00
Lionel Flandrin
482e7627f5 Implement GPU GP1: Soft Reset 2015-05-25 16:26:15 +02:00
Lionel Flandrin
29fe59ad0f Implement GPU GP0: Draw Mode 2015-05-25 16:26:15 +02:00
Lionel Flandrin
01b8f30705 Implemented basic GPU state and read from GPUSTAT register 2015-05-25 16:26:15 +02:00
Lionel Flandrin
50fab9e5ca Added travic CI support 2015-05-25 16:26:15 +02:00
Lionel Flandrin
af2ce7a955 Implement basic DMA support for OTC port 2015-05-25 16:26:15 +02:00
Lionel Flandrin
ca16f165af Handle illegal instructions 2015-05-25 16:26:15 +02:00
Lionel Flandrin
a942ae6e67 Implement LWCn and SWCn 2015-05-25 16:26:15 +02:00
Lionel Flandrin
7509a0e0a8 Implement SWL and SWR 2015-05-25 16:26:15 +02:00
Lionel Flandrin
e54b56aecd Implement LWL and LWR 2015-05-25 16:26:15 +02:00
Lionel Flandrin
1fea17da14 Panic when encountering a GTE instruction 2015-05-25 16:26:15 +02:00
Lionel Flandrin
216dcda25e Implement COP1 and COP3 opcodes 2015-05-25 16:26:15 +02:00
Lionel Flandrin
a0aad7d2c2 Implement XORI 2015-05-25 16:26:15 +02:00
Lionel Flandrin
c412f65ddf Implement SUB 2015-05-25 16:26:14 +02:00
Lionel Flandrin
599b0f20bf Implement MULT 2015-05-25 16:26:14 +02:00
Lionel Flandrin
257e4d44b6 Implement BREAK 2015-05-25 16:26:14 +02:00
Lionel Flandrin
37b9a6980b Implement XOR 2015-05-25 16:26:14 +02:00
Lionel Flandrin
f6c42a1e7c Set ready bits on GPUSTAT register to avoid deadlocking the BIOS. 2015-05-25 16:26:14 +02:00
Lionel Flandrin
cbdbbd25b4 Ignore access to IRQ control and timers 2015-05-25 16:26:14 +02:00
Lionel Flandrin
3b94d8390a Ignore reads and writes from/to the GPU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
13a30be089 Implement MULTU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
4206b331b9 Implement SRLV 2015-05-25 16:26:14 +02:00
Lionel Flandrin
731ea64cdf Implement SRAV 2015-05-25 16:26:14 +02:00
Lionel Flandrin
ebbcd0e9e0 Implement NOR 2015-05-25 16:26:14 +02:00
Lionel Flandrin
fa1b9d4b3e Implement LH 2015-05-25 16:26:14 +02:00
Lionel Flandrin
b809b2d9ee Implement SLLV 2015-05-25 16:26:14 +02:00
Lionel Flandrin
5da2eabe96 Implement 16bit load from RAM 2015-05-25 16:26:14 +02:00
Lionel Flandrin
c71e6687d2 Implement LHU 2015-05-25 16:26:14 +02:00
Lionel Flandrin
1e97374db6 Ignore read and writes from/to DMA 2015-05-25 16:26:14 +02:00
Lionel Flandrin
048981061d Implement RAM 16bit store 2015-05-25 16:26:14 +02:00
Lionel Flandrin
5428383153 Trigger an exception when the PC is not correctly aligned 2015-05-25 16:26:14 +02:00
Lionel Flandrin
e993ec9307 Generate exception on unaligned load/store 2015-05-25 16:26:14 +02:00
Lionel Flandrin
58e3216b74 Add overflow exception to ADD and ADDI 2015-05-25 16:26:14 +02:00
Lionel Flandrin
796794c46d Implement exceptions from branch delay slots 2015-05-25 16:26:14 +02:00
Lionel Flandrin
18e8224a5c Implement RFE 2015-05-25 16:26:14 +02:00