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125 commits 8 branches 2 tags 1.2 MiB
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Author SHA1 Message Date
Lionel Flandrin
7a0d58d448 Implement SPU register interface 2019-12-31 20:47:00 +00:00
Lionel Flandrin
f2870065b9 Implement SB and SH 2019-12-31 20:47:00 +00:00
Lionel Flandrin
cccbeb3a72 Implement ADDU 2019-12-31 20:47:00 +00:00
Lionel Flandrin
7524e6b124 Implement SLTU 2019-12-31 20:47:00 +00:00
Lionel Flandrin
bcf5e49102 Implement RAM 2019-12-31 20:46:58 +00:00
Lionel Flandrin
e1fad5767d Implement LW and load delay slots 2019-12-30 20:20:38 +00:00
Lionel Flandrin
02c635360e Implement ADDI 2019-12-29 20:40:25 +00:00
Lionel Flandrin
97f25d4f71 Implement BNE 2019-12-29 20:40:25 +00:00
Lionel Flandrin
76a9776648 Implement cache isolation 2019-12-29 20:40:25 +00:00
Lionel Flandrin
0998d66029 Implement MTC0 2019-12-29 20:40:25 +00:00
Lionel Flandrin
078af9b390 Implement COP0 instruction decoding 2019-12-29 20:40:25 +00:00
Lionel Flandrin
69daf8cec8 Implemented CACHE_CONTROL register 2019-12-29 20:40:25 +00:00
Lionel Flandrin
ba67444773 Implemented OR 2019-12-29 20:40:25 +00:00
Lionel Flandrin
803332124c Implemented J and branch delay slots 2019-12-29 20:40:25 +00:00
Lionel Flandrin
491b3a74e0 Implemented RAM_SIZE register 2019-12-29 20:40:25 +00:00
Lionel Flandrin
dd03fbf32c Implemented ADDIU 2019-12-29 20:40:25 +00:00
Lionel Flandrin
333ff020ad Implement SLL 2019-12-29 20:40:25 +00:00
Lionel Flandrin
8470d3f41a Implement MEM_CONTROL registers 2019-12-29 20:40:25 +00:00
Lionel Flandrin
66175a048d Implement SW 2019-12-29 20:40:25 +00:00
Lionel Flandrin
acf2b4adee Implement ORI 2019-12-29 20:40:25 +00:00
Lionel Flandrin
2c3062e720 Implement LUI 2019-12-29 20:40:25 +00:00
Lionel Flandrin
2564a84f20 Implement instruction decoding framework 2019-12-29 20:40:25 +00:00
Lionel Flandrin
93690bc74b Implement BIOS loading, reach the first instruction 2019-12-29 20:40:22 +00:00
Lionel Flandrin
4562d2ce8a Added .gitlab-ci.yml 
Based on https://chrismacnaughton.com/blog/rust/rust-gitlab-ci/
 2019-12-26 22:16:38 +00:00
Lionel Flandrin
55d54eff28 Initial commit 2019-12-25 20:15:39 +00:00