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Author	SHA1	Message	Date
Lionel Flandrin	afa4140939	CPU: implement MULT and MULTU timings	2020-01-19 20:10:01 +00:00
Lionel Flandrin	5dc26b5e26	CPU: implement interrupt handling	2020-01-19 00:22:08 +00:00
Lionel Flandrin	d28c78da74	DMA: fix bogus code that used outdated channel control value	2020-01-19 00:08:28 +00:00
Lionel Flandrin	4449fde0f4	DMA: implement end-of-dma interrupt	2020-01-18 23:57:19 +00:00
Lionel Flandrin	c943477778	GPU: implement clip, offset, texture window and mask configuration commands	2020-01-18 18:54:00 +00:00
Lionel Flandrin	f3151602b2	DMA: copy timing code from mednafen	2020-01-18 01:02:29 +00:00
Lionel Flandrin	7d71f505f9	DMA: complete register interface	2020-01-15 22:00:12 +00:00
Lionel Flandrin	9dbf9691e4	Implement DMA direction register	2020-01-15 21:51:39 +00:00
Lionel Flandrin	17147c13e2	DMA: implement reading channel control register	2020-01-15 21:32:19 +00:00
Lionel Flandrin	ff16c1e67c	Update psx.frame_done when the GPU is done rendering a frame	2020-01-15 21:22:50 +00:00
Lionel Flandrin	b64e531278	Implement GP1[0x08] (set draw mode)	2020-01-15 21:10:42 +00:00
Lionel Flandrin	633d572754	GPU: implement GP1, stub GPUREAD register	2020-01-15 21:03:32 +00:00
Lionel Flandrin	ab0888805c	DMA: start implementing channel configuration	2020-01-15 17:57:42 +00:00
Lionel Flandrin	b3552556ad	GPU: implement NOP	2020-01-15 17:09:47 +00:00
Lionel Flandrin	bd9d19be37	DMA: start implementing register interface	2020-01-14 20:16:15 +00:00
Lionel Flandrin	8f5fde1c12	Timers: implement GPU synchronization	2020-01-14 18:45:26 +00:00
Lionel Flandrin	10d5f9ac72	Improve event handling accuracy	2020-01-14 16:25:12 +00:00
Lionel Flandrin	07c539b25c	Remove unnecessary public functions and variables, improve docs	2020-01-14 16:17:00 +00:00
Lionel Flandrin	a419e29f32	Timers: increase default sync delay, improve comments	2020-01-14 14:32:02 +00:00
Lionel Flandrin	f78ef920a2	Timers: implement running from CPU	2020-01-14 00:39:51 +00:00
Lionel Flandrin	3f012f83ae	Timer: implement register reading	2020-01-13 23:41:33 +00:00
Lionel Flandrin	73cb1b111b	Timers: implemented register writes and sync prediction	2020-01-13 23:26:08 +00:00
Lionel Flandrin	ebca69d56c	GPU: fix clippy complaints regarding casts	2020-01-13 00:08:09 +00:00
Lionel Flandrin	1ccae9708e	Implement GPU IRQ trigger	2020-01-13 00:00:21 +00:00
Lionel Flandrin	efab9ad356	GPU: complete status register	2020-01-12 23:30:12 +00:00
Lionel Flandrin	e4afa0e8da	GPU: ported most video timings from mednafen	2020-01-12 21:54:03 +00:00
Lionel Flandrin	b7666b7e91	GPU: implement line timings	2020-01-12 20:50:36 +00:00
Lionel Flandrin	af5c4ea86d	GPU: put FIFO code in its own file	2020-01-12 17:25:52 +00:00
Lionel Flandrin	c8c516bc81	Implemented GPU clock	2020-01-12 15:46:18 +00:00
Lionel Flandrin	91191040f0	Add event handling framework	2020-01-12 14:48:34 +00:00
Lionel Flandrin	34738aaf6c	GPU: implement Draw Mode	2020-01-12 14:10:28 +00:00
Lionel Flandrin	a43ada0aa1	GPU: implement process_commands	2020-01-08 21:52:27 +00:00
Lionel Flandrin	7df313c3c0	Implement GPU command FIFO	2020-01-08 20:44:02 +00:00
Lionel Flandrin	67bd48b2cc	SPU: increment capture_index to update SPUSTAT correctly	2020-01-08 17:35:42 +00:00
Lionel Flandrin	8ebda4541a	Fix small MTC0 timing discrepency with mednafen	2020-01-08 17:27:58 +00:00
Lionel Flandrin	cd430396b8	Implement SPU STATUS register	2020-01-08 16:55:50 +00:00
Lionel Flandrin	301459d918	Implement synchronization architecture	2020-01-08 14:26:59 +00:00
Lionel Flandrin	2e01d3e5a5	More SPU registers, some cleanup	2020-01-08 12:50:50 +00:00
Lionel Flandrin	4e87922c29	Started implementing SPU voice configuration	2020-01-08 00:44:52 +00:00
Lionel Flandrin	e318f862d7	Implement SPU RAM write	2020-01-08 00:21:31 +00:00
Lionel Flandrin	1ea800796f	Started implementing SPU register map	2020-01-07 22:26:39 +00:00
Lionel Flandrin	e0982565d0	Implement DIV and DIVU timings	2020-01-07 01:27:39 +00:00
Lionel Flandrin	a14f889ed5	Implemented CPU timings using mednafen as reference	2020-01-07 01:27:39 +00:00
Lionel Flandrin	21d992f216	Implemented CPU instruction cache	2020-01-07 01:27:39 +00:00
Lionel Flandrin	6976e704a7	Reformat opcode arrays for better readability ... Rustfmt did a pretty terrible job with those and since we shouldn't have any unimplemented opcode anymore it makes sense to reformat them once and for all.	2020-01-07 01:27:39 +00:00
Lionel Flandrin	bdbeddca39	Implement LWC0, 1, 2 and 3 ... All CPU instructions are now implemented (or at least stubbed)	2020-01-07 01:27:39 +00:00
Lionel Flandrin	304d3accbd	Implement LWC0, 1, 2 and 3	2020-01-07 01:27:39 +00:00
Lionel Flandrin	d99d903916	Implement SWL and SWR	2020-01-07 01:27:39 +00:00
Lionel Flandrin	631a590263	Implement illegal instructions	2020-01-07 01:27:39 +00:00
Lionel Flandrin	41d89eafa0	Implement LWL and LWR	2020-01-07 01:27:39 +00:00