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Author	SHA1	Message	Date
Lionel Flandrin	e4afa0e8da	GPU: ported most video timings from mednafen	2020-01-12 21:54:03 +00:00
Lionel Flandrin	b7666b7e91	GPU: implement line timings	2020-01-12 20:50:36 +00:00
Lionel Flandrin	af5c4ea86d	GPU: put FIFO code in its own file	2020-01-12 17:25:52 +00:00
Lionel Flandrin	c8c516bc81	Implemented GPU clock	2020-01-12 15:46:18 +00:00
Lionel Flandrin	91191040f0	Add event handling framework	2020-01-12 14:48:34 +00:00
Lionel Flandrin	34738aaf6c	GPU: implement Draw Mode	2020-01-12 14:10:28 +00:00
Lionel Flandrin	a43ada0aa1	GPU: implement process_commands	2020-01-08 21:52:27 +00:00
Lionel Flandrin	7df313c3c0	Implement GPU command FIFO	2020-01-08 20:44:02 +00:00
Lionel Flandrin	67bd48b2cc	SPU: increment capture_index to update SPUSTAT correctly	2020-01-08 17:35:42 +00:00
Lionel Flandrin	8ebda4541a	Fix small MTC0 timing discrepency with mednafen	2020-01-08 17:27:58 +00:00
Lionel Flandrin	cd430396b8	Implement SPU STATUS register	2020-01-08 16:55:50 +00:00
Lionel Flandrin	301459d918	Implement synchronization architecture	2020-01-08 14:26:59 +00:00
Lionel Flandrin	2e01d3e5a5	More SPU registers, some cleanup	2020-01-08 12:50:50 +00:00
Lionel Flandrin	4e87922c29	Started implementing SPU voice configuration	2020-01-08 00:44:52 +00:00
Lionel Flandrin	e318f862d7	Implement SPU RAM write	2020-01-08 00:21:31 +00:00
Lionel Flandrin	1ea800796f	Started implementing SPU register map	2020-01-07 22:26:39 +00:00
Lionel Flandrin	e0982565d0	Implement DIV and DIVU timings	2020-01-07 01:27:39 +00:00
Lionel Flandrin	a14f889ed5	Implemented CPU timings using mednafen as reference	2020-01-07 01:27:39 +00:00
Lionel Flandrin	21d992f216	Implemented CPU instruction cache	2020-01-07 01:27:39 +00:00
Lionel Flandrin	6976e704a7	Reformat opcode arrays for better readability ... Rustfmt did a pretty terrible job with those and since we shouldn't have any unimplemented opcode anymore it makes sense to reformat them once and for all.	2020-01-07 01:27:39 +00:00
Lionel Flandrin	bdbeddca39	Implement LWC0, 1, 2 and 3 ... All CPU instructions are now implemented (or at least stubbed)	2020-01-07 01:27:39 +00:00
Lionel Flandrin	304d3accbd	Implement LWC0, 1, 2 and 3	2020-01-07 01:27:39 +00:00
Lionel Flandrin	d99d903916	Implement SWL and SWR	2020-01-07 01:27:39 +00:00
Lionel Flandrin	631a590263	Implement illegal instructions	2020-01-07 01:27:39 +00:00
Lionel Flandrin	41d89eafa0	Implement LWL and LWR	2020-01-07 01:27:39 +00:00
Lionel Flandrin	7ada2fe78e	Implement COP1, COP2 and stub COP2 (GTE)	2020-01-07 01:27:39 +00:00
Lionel Flandrin	72f260ccbb	Implement DMA registers	2020-01-07 01:27:39 +00:00
Lionel Flandrin	675b4b945c	Implement RFE	2020-01-07 01:27:39 +00:00
Lionel Flandrin	c081e87235	Attempt to catch panics inside of examine to make debugging more robust	2020-01-07 01:27:39 +00:00
Lionel Flandrin	3c0a6e06d5	Tweak IRQ read to match mednafen	2020-01-07 01:27:39 +00:00
Lionel Flandrin	48d7fd63c1	Added GDB helper script	2020-01-07 01:27:39 +00:00
Lionel Flandrin	85843150ac	Improve debugger interface	2020-01-07 01:27:39 +00:00
Lionel Flandrin	39168f8dd8	gitlab-ci: don't allow clippy failure	2020-01-07 01:27:39 +00:00
Lionel Flandrin	991073d48c	Imported Rustation's debugger with GDB TCP interface	2020-01-07 01:27:39 +00:00
Lionel Flandrin	b7c04558a2	Add proper logging facilities	2020-01-07 01:27:39 +00:00
Lionel Flandrin	78464d15e9	Implemented debugger interface ... No debugger backend yet. The interface is hidden behind the "debugger" feature, disabled by default for performance reasons.	2020-01-07 01:27:39 +00:00
Lionel Flandrin	5c523234cb	Implement exception where they weren't handled	2020-01-07 01:27:39 +00:00
Lionel Flandrin	c1f7b5e9b5	Implement exceptions, SYSCALL and BREAK	2020-01-07 01:27:39 +00:00
Lionel Flandrin	76d9f57954	Enable optimizations even for non-release builds ... The emulator will soon become unusable without optimizations anyway.	2020-01-07 01:27:39 +00:00
Lionel Flandrin	f677a9ab60	Implement timer registers	2020-01-07 01:27:39 +00:00
Lionel Flandrin	c495f57dae	Implement MFHI, MTHI, MFLO, MTLO	2020-01-07 01:27:39 +00:00
Lionel Flandrin	ab76637ad0	Implement MULT, MULTU, DIV and DIVU	2020-01-07 01:27:39 +00:00
Lionel Flandrin	c719acbcc9	Implement SRL, SRA, SLLV, SRLV and SRAV	2020-01-07 01:27:39 +00:00
Lionel Flandrin	7960f414d5	Implement SLT, SLTI and SLTIU	2020-01-07 01:27:39 +00:00
Lionel Flandrin	a3cdfcbf7e	Remove CPU state dump after every cycle	2020-01-07 01:27:39 +00:00
Lionel Flandrin	ff613a260a	Implement BXX	2020-01-07 01:27:39 +00:00
Lionel Flandrin	371fbd44c4	Implement IRQ registers	2020-01-07 01:27:39 +00:00
Lionel Flandrin	aad56c9a7d	Implement ADD, SUB and SUBU	2020-01-07 01:27:37 +00:00
Lionel Flandrin	cfdb8aa438	Implement AND, XOR and NOR	2019-12-31 20:47:00 +00:00
Lionel Flandrin	a3fd1e7f1b	Implement MFC0	2019-12-31 20:47:00 +00:00