Serial Interface
The base address of interface registers is CC006400.
All registers are 32-bit.
SI Channel 0 Output Buffer
CC006400
SIC0OUTBUF :
Bits Mnemonic Type Reset Description
31:24 R 0 Reserved
23:16 CMD RW 0 Command: This byte is the opcode for the command
sent to the controller during each command/response
packet. This is the first data byte sent from the SI I/F to
the game controller in the command/response packet.
15:8 OUTPUT0 RW 0 Output Byte 0: This is the first data byte of the
command packet. It is the second data byte sent from
the SI I/F to the game controller in the
command/response packet.
7:0 OUTPUT1 RW 0 Output Byte 1: This is the second databyte of the
command packet. It is the third data byte sent from the
SI I/F to the game controller in the command/response packet.
This register is double buffered, so main processor writes to the
SIC0OUTBUF will not interfere with the serial interface output
transfer. Internally, a second buffer is used to hold the output data to be
transferred across the serial interface. To check if SIC0OUTBUF
has been transferred to the second buffer, main processor polls the
SISR[WRST0] register. When SICOOUTBUF is transferred, SISR[WRST0] is cleared.
SI Channel 0 Input Buffer High
CC006404
SIC0INBUFH:
Bits Mnemonic Type Reset Description
31 ERRSTAT R 0 Error Status: This bit represents the current error status
for the last SI polling transfer on channel 0. This
register is updated after each polling transfer on this channel.
0 = No error on last transfer
1 = Error on last transfer
30 ERRLATCH R 0 Error Latch: This bit is an error status summary of the
SISR error bits for this channel. If an error has
occurred on a past SI transfer on channel 0 (polling or
Com transfer), this bit will be set. To determine the
exact error, read the SISR register. This bit is actually
an `or` of the latched error status bits for channel 0 in
the SISR. The bit is cleared by clearing the appropriate
error status bits latched in the SISR. The no response
error indicates that a controller is not present on this channel.
0 = No errors latched
1 = Error latched. Check SISR.
29:24 INPUT0 R Input Byte 0: This is the first data byte of the response
packet sent from the game controller to the SI I/F for
channel 0. The top two bits of the byte returning from
the controller are assumed to be `0`, so they are not
included.
23:16 INPUT1 R Input Byte 1: This is the second data byte of the
response packet sent from the game controller to the SI
I/F for channel 0.
15:8 INPUT2 R Input Byte 2: This is the third data byte of the response
packet sent from the game controllers to the SI I/F for
channel 0.
7:0 INPUT3 R Input Byte 3: This is the fourth data byte of the
response packet sent from the game controller to the SI
I/F for channel 0.
SIC0INBUFH and SIC0INBUFL are double buffered to prevent
inconsistent data reads due to main processor conflicting with incoming
serial interface data. To insure data read from SIC0INBUFH and
SIC0INFUBL are consistent, a locking mechanism prevents the double buffer from
copying new data to these registers. Once SIC0INBUFH is read, both SIC0INBUFH
and SIC0INBUFL are `locked` until SIC0INBUFL is read. While the buffers are
`locked`, new data is not copied into the buffers. When SIC0INBUFL is read, the
buffers become unlocked again.
SIC0INBUF SI Channel 0 Input Buffer Low
Mnemonic: SIC0INBUFL
Offset: 0x08
Size 32 bits SIC0INBUFL
Bits Mnemonic Type Reset Description
31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
SIC1INBUFH[INPUT1].
23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
SIC1INBUFH[INPUT1].
15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
SIC1INBUFH[INPUT1].
7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
SIC1INBUFH[INPUT1].
SIC1OUTBUF SI Channel 1 Output Buffer
Mnemonic: SIC 1
OUTBUF
Offset: 0x0C
Size 32 bits SIC1OUTBUF
Bits Mnemonic Type Reset Description
31:24 R 0 .times. 0 Reserved
23:16 CMD RW 0 .times. 0 Command: For SI channel 1. See
SIC0OUTBUFF[CMD]
description.
15:8 OUTPUT0 RW 0 .times. 0 Output Byte 0: For SI channel 1. See
SIC0OUTBUFF[OUTPUT0
description.
7:0 OUTPUT1 RW 0 .times. 0 Output Byte 1: For SI channel 1. See
SIC0OUTBUFF[OUTPUT1]
description.
SIC1INBUF SI Channel 1 Input Buffer High
Mnemonic:
SIC1INBUFH
Offset: 0x10
Size 32 bits SIC1INBUFH
Bits Mnemonic Type Reset Description
31 ERRSTAT R 0 .times. 0 Error Status: See Description of
SIC0INBUFH[ERRSTAT].
30 ERRLATCH R 0 .times. 0 Error Latch: See Description of
SIC0INBUFH[ERRLATCH].
29:24 INPUT0 R 0 .times. 0 Input Byte 0: See Description of
SIC0INBUFH[INPUT0].
23:16 INPUT1 R 0 .times. 0 Input Byte 1: See Description of
SIC0INBUFH[INPUT1].
15:8 INPUT2 R 0 .times. 0 Input Byte 2: See Description of
SIC0INBUFH[INPUT1].
7:0 INPUT3 R 0 .times. 0 Input Byte 3: See Description of
SIC0INBUFH[INPUT1].
SIC1INBUF SI Channel 1 Input Buffer Low
Mnemonic:
SIC1INBUFL
Offset: 0x14
Size 32 bits SIC1INBUFL
Bits Mnemonic Type Reset Description
31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
SIC0INBUFH[INPUT1].
23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
SIC0INBUFH[INPUT1].
15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
SIC0INBUFH[INPUT1].
7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
SIC0INBUFH[INPUT1].
SIC2OUTBUF SI Channel 2 Output Buffer
Mnemonic: SIC2OBUF
Offset: 0x18
Size 32 bits SIC2OUTBUF
Bits Mnemonic Type Reset Description
31:24 R 0 .times. 0 Reserved
23:16 CMD RW 0 .times. 0 Command: For SI Channel 2. See
SIC0OUTBUFF[CMD]
description
15:8 OUTPUT0 RW 0 .times. 0 Output Byte 0: For SI channel 2. See
SIC0OUTBUFF[OUTPUT0]
description.
7:0 OUTPUT1 RW 0 .times. 0 Output Byte 1: For SI channel 2. See
SIC0OUTBUFF[OUTPUT1]
description.
SIC2INBUF SI Channel 2 Input Buffer High
Mnemonic:
SIC2INBUFH
Offset: 0x1C
Size 32 bits SIC2INBUFH
Bits Mnemonic Type Reset Description
31 ERRSTAT R 0 .times. 0 Error Status: See Description of
SIC0INBUFH[ERRSTAT].
30 ERRLATCH R 0 .times. 0 Error Latch: See Description of
SIC0INBUFH[ERRLATCH].
29:24 INPUT0 R 0 .times. 0 Input Byte O: See Description of
SIC0INBUFH[INPUT1].
23:16 INPUT1 R 0 .times. 0 Input Byte 1: See Description of
SIC0INBUFH[INPUT0].
15:8 INPUT2 R 0 .times. 0 Input Byte 2: See Description of
SIC0INBUFH[INPUT1].
7:0 INPUT3 R 0 .times. 0 Input Byte 3: See Description of
SIC0INBUFH[INPUT1].
SIC2INBUF SI Channel 2 Input Buffer Low
Mnemonic:
SIC2INBUFL
Offset: 0x20
Size 32 bits SIC2INBUFL
Bits Mnemonic Type Reset Description
31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
SIC0INBUFH[INPUT0].
23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
SIC0INBUFH[INPUT0].
15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
SIC0INBUFH[INPUT0].
7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
SIC0INBUFH[INPUT0].
SIC30UTBUF SI Channel 3 Output Buffer
Mnemonic: SIC3OBUF
Offset: 0x24
Size 32 bits SIC3OUTBUF
Bits Mnemonic Type Reset Description
31:24 R 0 .times. 0 Reserved
23:16 CMD RW 0 .times. 0 Command: For SI channel 3. See
SIC0OUTBUFF[CMD0]
description
15:8 OUTPUT0 RW 0 .times. 0 Output Byte 0: For SI channel 3. See
SIC0OUTBUFF[OUTPUT0]
description
7:0 OUTPUT1 RW 0 .times. 0 Output Byte 1: For SI channel 3. See
SIC0OUTBUFF[OUTPUT1]
description
SIC3INBUF SI Channel 3 Input Buffer High
Mnemonic:
SIC3INBUFH
Offset: 0x28
Size 32 bits SIC3INBUFH
Bits Mnemonic Type Reset Description
31 ERRSTAT R 0 .times. 0 Error Status: See Description of
SIC0INBUFH[ERRSTAT].
30 ERRLATCH R 0 .times. 0 Error Latch: See Description of
SIC0INBUFH[ERRLATCH].
29:24 INPUT0 R 0 .times. 0 Input Byte 0: See Description of
SIC0INBUFH[INPUT0].
23:16 INPUT1 R 0 .times. 0 Input Byte 1: See Description of
SIC0INBUFH[INPUT1].
15:8 INPUT2 R 0 .times. 0 Input Byte 2: See Description of
SIC0INBUFH[INPUT1]
7:0 INPUT3 R 0 .times. 0 Input Byte 3: See Description of
SIC0INBUFH[INPUT1].
SIC3INBUF SI Channel 3 Input Buffer Low
Mnemonic:
SIC3INBUFL
Offset: 0x2C
Size 32 bits SIC4INBUFL
Bits Mnemonic Type Reset Description
31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
SIC0INBUFH[INPUT1].
23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
SIC0INBUFH[INPUT1].
15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
SIC0INBUFH[INPUT1].
7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
SIC0INBUFH[INPUT1].
SIPOLL SI Poll Register
Mnemonic: SIPOLL
Offset:
0x30
Size 32 bits SIPOLL
Bits Mnemonic Type Reset Description
31:26 R 0 .times. 0 Reserved
25:16 X RW 0 .times. 07 X lines register: determines the
number of horizontal
video lines between polling (the polling
interval).
The polling begins at vsync. 0 .times. 07
is the minimum
setting (determined by the time required to
complete
a single polling of the controller). The
maximum
setting depends on the current video mode
(number of
lines per vsync) and the SIPOLL[Y]
register. This
register takes affect after vsync.
15:8 Y RW 0 .times. 0 Y times register: This register
determines the number
of times the SI controllers are polled in a
single
frame. This register takes affect after
vsync.
7 EN0 RW 0 .times. 0 Enable channel 0: Enable polling of
channel 0.
When the channel is enabled, polling begins
at the
next vblank. When the channel is disabled,
polling is
stopped immediately after the current
transaction.
The status of this bit does not affect
communication
RAM transfers on this channel.
1 = Polling of channel 0 is enabled
0 = Polling of channel 0 is disabled
6 EN1 RW 0 .times. 0 Enable channel 1: See description for
SIPOLL[EN0].
5 EN2 RW 0 .times. 0 Enable channel 2: See Description for
SIPOLL[EN0].
4 EN3 RW 0 .times. 0 Enable channel 3: See Description for
SIPOLL[EN0].
3 VBCPY0 RW 0 .times. 0 Vblank copy output channel 0: Normally
main
processor writes to the SIC0OUTBUF register
are
copied immediately to the channel 0 output
buffer if a
transfer is not currently in progress. When
this bit is
asserted, main processor writes to channel
0's
SIC0OUTBUF will only be copied to the
outbuffer
on vblank. This is used to control the
timing of
commands to 3D LCD shutter glasses
connected to
the VI.
1 = Copy SIC0OUTBUF to output buffer only
on
vblank.
0 = Copy SIC0OUTBUF to output buffer after
writing.
2 VBCPY1 RW 0 .times. 0 Vblank copy output channel 1: See
Description for
SIPOLL[VBCPY0].
1 VBCPY2 RW 0 .times. 0 Vblank copy output channel 2: See
Description for
SIPOLL[VBCPY0].
0 VBCPY3 RW 0 .times. 0 Vblank copy output channel 3: See
Description for
SIPOLL[VBCPY0].
SICOMCSR SI Communication Control Status Register
Mnemonic: SICOMCSR
Offset: 0x34
Size 32 bits SICOMCSR
Bits Mnemonic Type Reset Description
31 TCINT RWC 0 .times. 0 Transfer Complete Interrupt Status
and clear. On
read this bit indicates the current
status of the
communication transfer complete
interrupt. When a
`1` is written to this register, the
interrupt is cleared.
Write:
0 = No effect
1 = Transfer Complete Interrupt
Read:
0 = Transfer Complete Interrupt not
requested
1 = Transfer Complete Interrupt has been
requested
30 TCINTMSK RW 0 .times. 0 Transfer Complete Interrupt Mask:
Interrupt masking
prevents the interrupt from being sent to
the main
processor, but does not affect the
assertion of
SICOMCSR[TCINT]
0 = Interrupt masked
1 = Interrupt enabled
29 COMERR R 0 .times. 0 Communication Error: This indicates
whether the
last SI communication transfer had an
error. See SiSr
for the cause of the error.
0 = No
1 = Error on transfer
28 RDSTINT R 0 .times. 0 Read Status Interrupt Status and
clear. On read this
bit indicates the current status of the
Read Status
interrupt. The interrupt is set whenever
SISR[RDSTn] bits are set. The interrupt
is cleared
when all of the RdSt bits in the SISR are
cleared by
reading from the Si Channel Input
Buffers. This
interrupt can be used to indicate that a
polling transfer
has completed and new data is captured in
the input
registers
Read:
0 = Transfer Complete Interrupt not
requested
1 = Transfer Complete Interrupt has been
requested
27 RDSTINTMSK RW 0 .times. 0 Read Status interrupt Mask:
Interrupt masking
prevents the interrupt from being sent to
the main
processor, but does not affect the
assertion of
SICOMCSR[RDSTINT]
0 = Interrupt masked
1 = Interrupt enabled
26:23 R 0 .times. 0 Reserved
22:16 OUTLNGTH RW 0 .times. 0 Communication Channel Output Length
in bytes.
Minimum transfer is 1 byte. A value of 0
.times. 00 will
transfer 128 bytes. These bits should not
be modified
while SICOM transfer is in progress.
15 R 0 .times. 0 Reserved
14:8 INLNGTH RW 0 .times. 0 Communication Channel Output Length
in bytes.
Minimum transfer is 1 byte. A value of 0
.times. 00 will
transfer 128 bytes. These bits should not
be modified
while SICOM transfer is in progress.
2:1 CHANNEL RW 0 .times. 0 Channel: determines which SI
channel will be used
the communication interface.
00 = Channel 1
01 = Channel 2
10 = Channel 3
11 = Channel 4
These bits should not be modified while
SICOM
transfer is in progress.
0 TSTART RW 0 .times. 0 Transfer Start: When a `1` is
written to this register,
the current communication transfer is
executed. The
transfer begins immediately after the
current
transaction on this channel has
completed. When
read this bit represents the current
transfer status.
Once a communication transfer has been
executed,
polling will resume at the next vblank if
the channel's
SIPOLL[ENn] bit is set.
Write:
0 = Do not start command
1 = Start command
Read:
0 = Command Complete
1 = Command Pending
When programming the SICOMCSR after a SICOM transfers has already
started (e.g., SICOMCSR[TSTART] is set), the example software reads the current
value first, then and/or in the proper data and then write the new data back.
The software should not modify any of the transfer parameters (OUTLNGTH,
INLNGTH, CHANNEL) until the current transfer is complete. This is done to
prevent a SICOM transfer already in progress from being disturbed. When writing
the data back, the software should not set the TSTART bit again unless the
current transfer is complete and another transfer is required.
SISI SI
Status Register
Mnemonic: SISR
Offset: 0x38
Size 32 bits
SISR
Bits Mnemonic Type Reset Description
31 WR RW 0 .times. 0 Write SICnOUTBUF Register: This
register controls
and indicates whether the SICnOUTBUFs have
been
copied to the double buffered output buffers.
This bit
is cleared after the buffers have been
copied.
Write
1 = Copy all buffers
0 = No effect
Read
1 = Buffer not copied
0 = Buffer copied
30 R 0 .times. 0 Reserved
29 RDST0 R 0 .times. 0 Read Status SIC0OINBUF Register: This
register
indicates whether the SIC0INBUFs have been
captured new data and whether the data has
already
been read by the main processor (read
indicated by
main processor read of SIC01NBUF[ERRSTAT,
ERRLATCH, INPUT0, INPUT1)]
1 = New data available, not read by main
processor
0 = No new data available, already read by
main
processor
28 WRST0 R 0 .times. 0 Write Status SIC0OUTBUF Register: This
register
indicates whether the SIC0OUTBUFs have been
copied to the double buffered output buffers.
This bit
is cleared after the buffers have been
copied.
1 = Buffer not copied
0 = Buffer copied
27 NOREP0 RWC 0 .times. 0 No Response Error Channel 0: This
register indicates
that a previous transfer resulted in no
response from
the controller. This can also be used to
detect
whether a controller is connected. If no
controller is
connected, this bit will be set. Once set
this bit
remains set until it is cleared by the main
processor.
To clear this bit write `1` to this register.
Write:
0 = No effect
1 = Clear No Response Error
Read:
0 = No Response Error not asserted
1 = No Response Error asserted
26 COLL0 RWC 0 .times. 0 Collision Error Channel 0: This
register indicates
data collision between controller and main
unit.
Once set this bit remains set until it is
cleared by the
main processor. To clear this bit write `1`
to this
register.
Write:
0 = No effect
1 = Clear Collision Error
Read:
0 = Collision Error not asserted
1 = Collision Error asserted
25 OVRUN0 RWC 0 .times. 0 Over Run Error Channel 0: This register
indicates
that the main unit has received more data
than
expected. Once set this bit remains set until
it is
cleared by the main processor. To clear this
bit write
`1' to this register.
Write:
0 = No effect
1 = Clear Over Run Error
Read:
0 = Over Run Error not asserted
1 = Over Run Error asserted
24 UNRUN RWC 0 .times. 0 Under Run Error Channel 0: This
register indicates
that the main unit has received less data
than
expected. Once set this bit remain set until
it is.
cleared by the main processor. To clear this
bit write
`1` to this register.
Write:
0 = No effect
1 = Clear Under Run Error
Read:
0 = Under Run not asserted
1 = Under Run asserted
23:22 R 0 .times. 0 Reserved
21 RDST1 R 0 .times. 0 Read Status SIC1OINBUF Register: See
SISR[RDST0].
20 WRST1 R 0 .times. 0 Write Status SIC0OUTBUF Register: See
SISR[WRST0].
19 NOREP1 RWC 0 .times. 0 No Response Error Channel 1: See
SISR[NOREP0].
18 COLL1 RWC 0 .times. 0 Collision Error Channel 1: See
SISR[COLL0].
17 OVRUN1 RWC 0 .times. 0 Over Run Error Channel 1: See
SISR[OVRUN0].
16 UNRUN1 RWC 0 .times. 0 Under Run Error Channel 1: See
SISR[UNRUN0].
15:14 R 0 .times. 0 Reserved
13 RDST2 R 0 .times. 0 Read Status SIC1OINBUF Register: See
SISR[RDST2].
12 WRST2 R 0 .times. 0 Write Status SIC0OUTBUF Register: See
SISR[WRST2].
11 NOREP2 RWC 0 .times. 0 No Response Error Channel 2: See
SISR[NOREP0].
10 COLL2 RWC 0 .times. 0 Collision Error Channel 2: See
SISR[COLL0].
9 OVRUN2 RWC 0 .times. 0 Over Run Error Channel 2: See
SISR[OVRUN0].
8 UNRUN2 RWC 0 .times. 0 Under Run Error Channel 2: See
SISR[UNRUN0].
7:6 R 0 .times. 0 Reserved
5 RDST3 R 0 .times. 0 Read Status SIC1OINBUF Register: See
SISR[RDST2].
4 WRST3 R 0 .times. 0 Write Status SIC0OUTBUF Register: See
SISR[WRST2].
3 NOREP3 RWC 0 .times. 0 No Response Error Channel 3: See
SISR[NOREP0].
2 COLL3 RWC 0 .times. 0 Collision Error Channel 3: See
SISR[COLL0].
1 OVRUN3 RWC 0 .times. 0 Over Run Error Channel 3: See
SISR[OVRUN0].
0 UNRUN3 RWC 0 .times. 0 Under Run Error Channel 3: See
SISR[UNRUN0].
SIEXILK SI EXI Clock Lock
Mnemonic: SIEXILK
Offset: Ox3C
Size 32 bits SIEXILK
Bits Mnemonic Type Reset Description
31 LOCK RW 0 .times. 1 Lock: This bit prevents the main
processor from setting the EXI clock
frequencies to 32 MHz.
0 = EXI Clocks Unlocked, 32 MHz
EXICLK setting permitted.
1 = EXI Clock Locked, 32 MHz
EXICLK setting not permitted.
30:0 R 0 .times. 0 Reserved
FIG. 8D is an even more detailed overall view of
serial interface 1000 showing the details of serial
interface communication circuitry and registers 1012. Controllers 52a and 52b
(and 52c and 52d, if present) are connected to game console 54 via connector
ports 1002. Modem 1404 modulates and demodulates data transferred between the
controllers and the console. In the example system, communication between the
console and the controllers uses duty-cycle (pulse-width) modulation and the
data is communicated over one line. The communication is half-duplex. The byte
transfer order is "big-endian" in which within a given multi-byte numeric
representation, the most significant byte has the lowest address (i.e., the data
is transferred "big-end" first). Controller input/output buffer 1016 is used for
normal data transfers involving controllers 52a-52d. As shown in FIG. 8D,
input/output buffer 1016 is arranged as a double buffer. Communication RAM 1014
is provided for use in variable-size data transfers to and from controllers
52a-52d. In the example system, the maximum data size of these variable-size
data transfers is 32 words. Of course, the present invention is not limited in
this respect. Channel selector circuit 1408 controls selectors 1412a-1412d to
selectively connect modem 1404 to either communication RAM 1014 or input/output
buffer 1016. An HV counter latch circuit 1406 latches the screen position of a
flash signal when a trigger input is received from a light gun unit. In the
example system shown in FIG. 8, triggers inputs to the HV counter latch circuit
1406 are provided for connectors 1 and 2 only. It will be apparent that trigger
inputs may be provided for the other connectors if desired. HV counter latch
circuit 1406 may also be used with light pens connected to connectors 1 and/or
2.
Additional details of the serial interface may be found
in application Ser. No. 09/722,664 filed Nov. 28, 2000 of Shimuzu et al.
entitled "Controller Interface for a Graphics System", the contents of which are
incorporated herein.
Cut from USPTO #6609977
org - ogamespec@gmail.com