mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
480 lines
No EOL
11 KiB
C++
480 lines
No EOL
11 KiB
C++
#include "Common/ChunkFile.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "PpcRegCache.h"
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#include "ppcEmitter.h"
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#include "PpcJit.h"
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using namespace MIPSAnalyst;
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _SA ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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//#define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp
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{
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static u32 EvalOr(u32 a, u32 b) { return a | b; }
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static u32 EvalXor(u32 a, u32 b) { return a ^ b; }
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static u32 EvalAnd(u32 a, u32 b) { return a & b; }
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static u32 EvalAdd(u32 a, u32 b) { return a + b; }
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static u32 EvalSub(u32 a, u32 b) { return a - b; }
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static u32 EvalNor(u32 a, u32 b) { return ~(a | b); }
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// Utilities to reduce duplicated code
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void Jit::CompType3(int rd, int rs, int rt, void (PPCXEmitter::*arith)(PPCReg Rd, PPCReg Ra, PPCReg Rb), u32 (*eval)(u32 a, u32 b), bool isSub) {
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, (*eval)(gpr.GetImm(rs), gpr.GetImm(rt)));
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} else if (gpr.IsImm(rt)) {
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u32 rtImm = gpr.GetImm(rt);
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gpr.MapDirtyIn(rd, rs);
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MOVI2R(SREG, rtImm);
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(this->*arith)(gpr.R(rd), gpr.R(rs), SREG);
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} else if (gpr.IsImm(rs)) {
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u32 rsImm = gpr.GetImm(rs);
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gpr.MapDirtyIn(rd, rt);
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// TODO: Special case when rsImm can be represented as an Operand2
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MOVI2R(SREG, rsImm);
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(this->*arith)(gpr.R(rd), SREG, gpr.R(rt));
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} else {
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// Generic solution
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gpr.MapDirtyInIn(rd, rs, rt);
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(this->*arith)(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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}
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}
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void Jit::CompImmLogic(int rs, int rt, u32 uimm, void (PPCXEmitter::*arith)(PPCReg Rd, PPCReg Ra, unsigned short imm), u32 (*eval)(u32 a, u32 b))
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{
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if (gpr.IsImm(rs)) {
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gpr.SetImm(rt, (*eval)(gpr.GetImm(rs), uimm));
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} else {
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gpr.MapDirtyIn(rt, rs);
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(this->*arith)(gpr.R(rt), gpr.R(rs), uimm);
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}
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}
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void Jit::Comp_IType(u32 op)
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{
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CONDITIONAL_DISABLE;
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s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension
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u32 uimm = op & 0xFFFF;
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u32 suimm = (u32)(s32)simm;
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int rt = _RT;
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int rs = _RS;
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int o = op>>26;
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// noop, won't write to ZERO.
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if (rt == 0)
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return;
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switch (op >> 26)
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{
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case 8: // same as addiu?
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case 9: // R(rt) = R(rs) + simm; break; //addiu
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{
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if (gpr.IsImm(rs)) {
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gpr.SetImm(rt, gpr.GetImm(rs) + simm);
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} else {
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gpr.MapDirtyIn(rt, rs);
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ADDI(gpr.R(rt), gpr.R(rs), simm);
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}
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break;
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}
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// Use with caution can change CR0 !
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case 12: CompImmLogic(rs, rt, uimm, &PPCXEmitter::ANDI, &EvalAnd); break;
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// Safe
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case 13: CompImmLogic(rs, rt, uimm, &PPCXEmitter::ORI, &EvalOr); break;
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case 14: CompImmLogic(rs, rt, uimm, &PPCXEmitter::XORI, &EvalXor); break;
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case 15: // R(rt) = uimm << 16; //lui
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gpr.SetImm(rt, uimm << 16);
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break;
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/* https://github.com/gligli/mupen64-360/blob/master/source/r4300/ppc/MIPS-to-PPC.c#L1794 **/
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/*
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case 10: R(rt) = (s32)R(rs) < simm; break; //slti
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821ECC64 80EA0EB0 lwz r7,0EB0h(r10)
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821ECC68 5529103A slwi r9,r9,2
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821ECC6C 7D29382E lwzx r9,r9,r7
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821ECC70 7CC84810 subfc r6,r8,r9
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821ECC74 7D094A38 eqv r9,r8,r9
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821ECC78 55290FFE srwi r9,r9,31
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821ECC7C 7D290194 addze r9,r9
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821ECC80 556B103A slwi r11,r11,2
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821ECC84 552907FE clrlwi r9,r9,31
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821ECC88 7D2B392E stwx r9,r11,r7
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821ECC8C 48000070 b MIPSInt::Int_IType + 010ch (821eccfch)
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*/
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case 10: // slti - R(rt) = (s32)R(rs) < simm
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if (gpr.IsImm(rs))
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{
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gpr.SetImm(rt, (s32)gpr.GetImm(rs) < simm);
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break;
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} else {
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DISABLE;
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gpr.MapDirtyIn(rt, rs);
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PPCReg ppc_rt = gpr.R(rt);
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PPCReg ppc_rs = gpr.R(rs);
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MOVI2R(R0, 0);
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ADDI(SREG, R0, uimm);
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SUBFC(R0, SREG, ppc_rs);
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EQV(ppc_rt, SREG, ppc_rs);
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SRWI(ppc_rt, ppc_rt, 31);
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ADDZE(ppc_rt, ppc_rt);
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RLWINM(ppc_rt, ppc_rt, 0, 31, 31);
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//Break();
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break;
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}
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/*
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case 11: R(rt) = R(rs) < suimm; break; //sltiu
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821ECC90 80EA0EB0 lwz r7,0EB0h(r10)
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821ECC94 5529103A slwi r9,r9,2
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821ECC98 7D29382E lwzx r9,r9,r7
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821ECC9C 7D284810 subfc r9,r8,r9
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821ECCA0 7D294910 subfe r9,r9,r9
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821ECCA4 4BFFFFDC b MIPSInt::Int_IType + 0090h (821ecc80h)
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*/
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case 11: //sltiu
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if (gpr.IsImm(rs))
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{
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gpr.SetImm(rt, gpr.GetImm(rs) < uimm);
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break;
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} else {
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DISABLE;
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gpr.MapDirtyIn(rt, rs);
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PPCReg ppc_rt = gpr.R(rt);
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ADDI(SREG, R0, uimm);
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SUBFC(ppc_rt, SREG, gpr.R(rs));
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SUBFE(ppc_rt, ppc_rt, ppc_rt);
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NEG(ppc_rt, ppc_rt);
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break;
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}
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default:
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Comp_Generic(op);
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break;
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}
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}
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void Jit::Comp_RType2(u32 op) {
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Comp_Generic(op);
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}
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void Jit::Comp_RType3(u32 op) {
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CONDITIONAL_DISABLE;
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int rt = _RT;
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int rs = _RS;
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int rd = _RD;
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// noop, won't write to ZERO.
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if (rd == 0)
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return;
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u8 o = op & 63;
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switch (op & 63)
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{
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case 10: // if (R(rt) == 0) R(rd) = R(rs); break; //movz
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if (rd == rs)
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break;
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if (!gpr.IsImm(rt))
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{
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gpr.MapDirtyInIn(rd, rt, rs, false);
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CMPI(gpr.R(rt), 0);
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PpcGen::FixupBranch ptr;
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ptr = B_Cond(_BNE);
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MR(gpr.R(rd), gpr.R(rs));
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SetJumpTarget(ptr);
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}
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else if (gpr.GetImm(rt) == 0)
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{
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// Yes, this actually happens.
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if (gpr.IsImm(rs))
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gpr.SetImm(rd, gpr.GetImm(rs));
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else
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{
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gpr.MapDirtyIn(rd, rs);
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MR(gpr.R(rd), gpr.R(rs));
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}
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}
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break;
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case 11:// if (R(rt) != 0) R(rd) = R(rs); break; //movn
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if (rd == rs)
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break;
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if (!gpr.IsImm(rt))
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{
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gpr.MapDirtyInIn(rd, rt, rs, false);
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CMPI(gpr.R(rt), 0);
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PpcGen::FixupBranch ptr;
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ptr = B_Cond(_BEQ);
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MR(gpr.R(rd), gpr.R(rs));
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SetJumpTarget(ptr);
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}
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else if (gpr.GetImm(rt) != 0)
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{
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// Yes, this actually happens.
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if (gpr.IsImm(rs))
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gpr.SetImm(rd, gpr.GetImm(rs));
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else
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{
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gpr.MapDirtyIn(rd, rs);
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MR(gpr.R(rd), gpr.R(rs));
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}
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}
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break;
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case 32: //R(rd) = R(rs) + R(rt); break; //add
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case 33: //R(rd) = R(rs) + R(rt); break; //addu
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// Some optimized special cases
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if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0) {
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gpr.MapDirtyIn(rd, rt);
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MR(gpr.R(rd), gpr.R(rt));
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} else if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0) {
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gpr.MapDirtyIn(rd, rs);
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MR(gpr.R(rd), gpr.R(rs));
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} else {
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CompType3(rd, rs, rt, &PPCXEmitter::ADD, &EvalAdd);
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}
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break;
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case 34: //R(rd) = R(rs) - R(rt); break; //sub
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case 35: //R(rd) = R(rs) - R(rt); break; //subu
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CompType3(rd, rs, rt, &PPCXEmitter::SUB, &EvalSub, true);
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break;
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case 36: //R(rd) = R(rs) & R(rt); break; //and
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CompType3(rd, rs, rt, &PPCXEmitter::AND, &EvalAnd);
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break;
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case 37: //R(rd) = R(rs) | R(rt); break; //or
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CompType3(rd, rs, rt, &PPCXEmitter::OR, &EvalOr);
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break;
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case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
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CompType3(rd, rs, rt, &PPCXEmitter::XOR, &EvalXor);
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break;
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// Not tested !
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case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor
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CompType3(rd, rs, rt, &PPCXEmitter::NOR, &EvalNor);
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break;
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case 42: //R(rd) = (int)R(rs) < (int)R(rt); break; //slt
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, (s32)gpr.GetImm(rs) < (s32)gpr.GetImm(rt));
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} else {
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gpr.MapDirtyInIn(rd, rs, rt);
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PPCReg ppc_rd = gpr.R(rd);
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PPCReg ppc_rs = gpr.R(rs);
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PPCReg ppc_rt = gpr.R(rt);
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SUBFC(R0, ppc_rt, ppc_rs);
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EQV(ppc_rd, ppc_rt, ppc_rs);
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SRWI(ppc_rd, ppc_rd, 31);
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ADDZE(ppc_rd, ppc_rd);
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RLWINM(ppc_rd, ppc_rd, 0, 31, 31);
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}
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break;
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case 43: //R(rd) = R(rs) < R(rt); break; //sltu
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, gpr.GetImm(rs) < gpr.GetImm(rt));
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} else {
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gpr.MapDirtyInIn(rd, rs, rt);
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PPCReg ppc_rd = gpr.R(rd);
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SUBFC(ppc_rd, gpr.R(rt), gpr.R(rs));
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SUBFE(ppc_rd, ppc_rd, ppc_rd);
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NEG(ppc_rd, ppc_rd);
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}
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break;
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case 44:// R(rd) = ((s32)R(rs) > (s32)R(rt)) ? R(rs) : R(rt); break; //max
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// DISABLE;
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if (gpr.IsImm(rs) && gpr.IsImm(rt))
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gpr.SetImm(rd, std::max((s32)gpr.GetImm(rs), (s32)gpr.GetImm(rt)));
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else
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{
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gpr.MapDirtyInIn(rd, rs, rt);
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PpcGen::FixupBranch end;
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// by default rd = rs
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MR(gpr.R(rd), gpr.R(rs));
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// if rs > rt => end
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CMP(gpr.R(rs), gpr.R(rt));
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end = B_Cond(_BGT);
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// rd = rt
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MR(gpr.R(rd), gpr.R(rt));
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SetJumpTarget(end);
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//Break();
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}
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break;
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case 45:
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//DISABLE;
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if (gpr.IsImm(rs) && gpr.IsImm(rt))
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gpr.SetImm(rd, std::min((s32)gpr.GetImm(rs), (s32)gpr.GetImm(rt)));
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else
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{
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gpr.MapDirtyInIn(rd, rs, rt);
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PpcGen::FixupBranch end;
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// by default rd = rs
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MR(gpr.R(rd), gpr.R(rs));
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// if rs < rt => end
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CMP(gpr.R(rs), gpr.R(rt));
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end = B_Cond(_BLT);
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// rd = rt
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MR(gpr.R(rd), gpr.R(rt));
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SetJumpTarget(end);
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}
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break;
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default:
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Comp_Generic(op);
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break;
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}
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}
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void Jit::Comp_ShiftType(u32 op) {
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DISABLE;
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CONDITIONAL_DISABLE;
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int rs = _RS;
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int rd = _RD;
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int fd = _FD;
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int rt = _RT;
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int sa = _SA;
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// noop, won't write to ZERO.
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if (rd == 0)
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return;
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// WARNING : ROTR
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switch (op & 0x3f)
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{
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case 0: //sll
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//DISABLE;
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gpr.MapDirtyIn(rd, rt);
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//RLWINM(gpr.R(rd), gpr.R(rt), sa, 0, (31-sa));
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SLWI(gpr.R(rd), gpr.R(rt), sa);
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// Break();
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break;
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case 2: //srl
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//DISABLE;
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gpr.MapDirtyIn(rd, rt);
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SRWI(gpr.R(rd), gpr.R(rt), sa);
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// Break();
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break;
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case 3: //sra
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//DISABLE;
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gpr.MapDirtyIn(rd, rt);
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SRAWI(gpr.R(rd), gpr.R(rt), sa);
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break;
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case 4: //sllv
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//DISABLE;
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if (gpr.IsImm(rs))
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{
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int sa = gpr.GetImm(rs) & 0x1F;
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gpr.MapDirtyIn(rd, rt);
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RLWINM(gpr.R(rd), gpr.R(rt), sa, 0, (31-sa));
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break;
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}
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gpr.MapDirtyInIn(rd, rs, rt);
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ANDI(SREG, gpr.R(rs), 0x1F);
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SLW(gpr.R(rd), gpr.R(rt), SREG);
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break;
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case 6: //srlv
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// DISABLE;
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if (gpr.IsImm(rs))
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{
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int sa = gpr.GetImm(rs) & 0x1F;
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gpr.MapDirtyIn(rd, rt);
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RLWINM(gpr.R(rd), gpr.R(rt), (32-sa), sa, 31);
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break;
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}
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gpr.MapDirtyInIn(rd, rs, rt);
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ANDI(SREG, gpr.R(rs), 0x1F);
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SRW(gpr.R(rd), gpr.R(rt), SREG);
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break;
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case 7: //srav
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// DISABLE;
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if (gpr.IsImm(rs))
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{
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int sa = gpr.GetImm(rs) & 0x1F;
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gpr.MapDirtyIn(rd, rt);
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SRAWI(gpr.R(rd), gpr.R(rt), sa);
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break;
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}
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gpr.MapDirtyInIn(rd, rs, rt);
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ANDI(SREG, gpr.R(rs), 0x1F);
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SRAW(gpr.R(rd), gpr.R(rt), SREG);
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break;
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default:
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Comp_Generic(op);
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break;
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}
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}
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void Jit::Comp_Allegrex(u32 op) {
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Comp_Generic(op);
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}
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|
|
|
void Jit::Comp_Allegrex2(u32 op) {
|
|
Comp_Generic(op);
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|
}
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|
|
|
void Jit::Comp_MulDivType(u32 op) {
|
|
Comp_Generic(op);
|
|
}
|
|
|
|
void Jit::Comp_Special3(u32 op) {
|
|
Comp_Generic(op);
|
|
}
|
|
|
|
} |