mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
383 lines
12 KiB
C++
383 lines
12 KiB
C++
#include "Common/CommonFuncs.h"
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#include "Common/Log.h"
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#include "Core/MIPS/IR/IRInst.h"
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#include "Core/MIPS/MIPSDebugInterface.h"
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#include "Core/HLE/ReplaceTables.h"
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// Legend
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// ======================
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// _ = ignore
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// G = GPR register
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// C = 32-bit constant from array
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// c = 8-bit constant from array
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// I = immediate value from instruction
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// F = FPR register, single
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// V = FPR register, Vec4. Reg number always divisible by 4.
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// 2 = FPR register, Vec2 (uncommon)
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// v = Vec4Init constant, chosen by immediate
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// s = Shuffle immediate (4 2-bit fields, choosing a xyzw shuffle)
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// r = Replacement function (in constant field)
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//
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// WARNING: The IRJit compiler also uses these letters for semantic information!
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// So if you add new letters, don't forget to add them to IRNativeRegCacheBase::MappingFromInst.
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static const IRMeta irMeta[] = {
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{ IROp::Nop, "Nop", "" },
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{ IROp::SetConst, "SetConst", "GC" },
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{ IROp::SetConstF, "SetConstF", "FC" },
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{ IROp::Mov, "Mov", "GG" },
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{ IROp::Add, "Add", "GGG" },
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{ IROp::Sub, "Sub", "GGG" },
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{ IROp::Neg, "Neg", "GG" },
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{ IROp::Not, "Not", "GG" },
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{ IROp::And, "And", "GGG" },
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{ IROp::Or, "Or", "GGG" },
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{ IROp::Xor, "Xor", "GGG" },
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{ IROp::AddConst, "AddConst", "GGC" },
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{ IROp::OptAddConst, "OptAddConst", "GC" },
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{ IROp::SubConst, "SubConst", "GGC" },
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{ IROp::AndConst, "AndConst", "GGC" },
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{ IROp::OrConst, "OrConst", "GGC" },
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{ IROp::XorConst, "XorConst", "GGC" },
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{ IROp::OptAndConst, "OptAndConst", "GC" },
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{ IROp::OptOrConst, "OptOrConst", "GC" },
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{ IROp::Shl, "Shl", "GGG" },
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{ IROp::Shr, "Shr", "GGG" },
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{ IROp::Sar, "Sar", "GGG" },
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{ IROp::Ror, "Ror", "GGG" },
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{ IROp::ShlImm, "ShlImm", "GGI" },
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{ IROp::ShrImm, "ShrImm", "GGI" },
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{ IROp::SarImm, "SarImm", "GGI" },
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{ IROp::RorImm, "RorImm", "GGI" },
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{ IROp::Slt, "Slt", "GGG" },
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{ IROp::SltConst, "SltConst", "GGC" },
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{ IROp::SltU, "SltU", "GGG" },
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{ IROp::SltUConst, "SltUConst", "GGC" },
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{ IROp::Clz, "Clz", "GG" },
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{ IROp::MovZ, "MovZ", "GGG", IRFLAG_SRC3DST },
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{ IROp::MovNZ, "MovNZ", "GGG", IRFLAG_SRC3DST },
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{ IROp::Max, "Max", "GGG" },
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{ IROp::Min, "Min", "GGG" },
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{ IROp::BSwap16, "BSwap16", "GG" },
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{ IROp::BSwap32, "BSwap32", "GG" },
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{ IROp::Mult, "Mult", "_GG" },
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{ IROp::MultU, "MultU", "_GG" },
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{ IROp::Madd, "Madd", "_GG" },
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{ IROp::MaddU, "MaddU", "_GG" },
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{ IROp::Msub, "Msub", "_GG" },
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{ IROp::MsubU, "MsubU", "_GG" },
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{ IROp::Div, "Div", "_GG" },
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{ IROp::DivU, "DivU", "_GG" },
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{ IROp::MtLo, "MtLo", "_G" },
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{ IROp::MtHi, "MtHi", "_G" },
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{ IROp::MfLo, "MfLo", "G" },
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{ IROp::MfHi, "MfHi", "G" },
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{ IROp::Ext8to32, "Ext8to32", "GG" },
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{ IROp::Ext16to32, "Ext16to32", "GG" },
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{ IROp::ReverseBits, "ReverseBits", "GG" },
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{ IROp::Load8, "Load8", "GGC" },
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{ IROp::Load8Ext, "Load8", "GGC" },
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{ IROp::Load16, "Load16", "GGC" },
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{ IROp::Load16Ext, "Load16Ext", "GGC" },
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{ IROp::Load32, "Load32", "GGC" },
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{ IROp::Load32Left, "Load32Left", "GGC", IRFLAG_SRC3DST },
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{ IROp::Load32Right, "Load32Right", "GGC", IRFLAG_SRC3DST },
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{ IROp::Load32Linked, "Load32Linked", "GGC" },
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{ IROp::LoadFloat, "LoadFloat", "FGC" },
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{ IROp::LoadVec4, "LoadVec4", "VGC" },
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{ IROp::Store8, "Store8", "GGC", IRFLAG_SRC3 },
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{ IROp::Store16, "Store16", "GGC", IRFLAG_SRC3 },
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{ IROp::Store32, "Store32", "GGC", IRFLAG_SRC3 },
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{ IROp::Store32Left, "Store32Left", "GGC", IRFLAG_SRC3 },
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{ IROp::Store32Right, "Store32Right", "GGC", IRFLAG_SRC3 },
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{ IROp::Store32Conditional, "Store32Conditional", "GGC", IRFLAG_SRC3DST },
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{ IROp::StoreFloat, "StoreFloat", "FGC", IRFLAG_SRC3 },
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{ IROp::StoreVec4, "StoreVec4", "VGC", IRFLAG_SRC3 },
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{ IROp::FAdd, "FAdd", "FFF" },
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{ IROp::FSub, "FSub", "FFF" },
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{ IROp::FMul, "FMul", "FFF" },
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{ IROp::FDiv, "FDiv", "FFF" },
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{ IROp::FMin, "FMin", "FFF" },
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{ IROp::FMax, "FMax", "FFF" },
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{ IROp::FMov, "FMov", "FF" },
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{ IROp::FSqrt, "FSqrt", "FF" },
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{ IROp::FSin, "FSin", "FF" },
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{ IROp::FCos, "FCos", "FF" },
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{ IROp::FSqrt, "FSqrt", "FF" },
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{ IROp::FRSqrt, "FRSqrt", "FF" },
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{ IROp::FRecip, "FRecip", "FF" },
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{ IROp::FAsin, "FAsin", "FF" },
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{ IROp::FNeg, "FNeg", "FF" },
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{ IROp::FSign, "FSign", "FF" },
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{ IROp::FAbs, "FAbs", "FF" },
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{ IROp::FRound, "FRound", "FF" },
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{ IROp::FTrunc, "FTrunc", "FF" },
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{ IROp::FCeil, "FCeil", "FF" },
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{ IROp::FFloor, "FFloor", "FF" },
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{ IROp::FCvtWS, "FCvtWS", "FF" },
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{ IROp::FCvtSW, "FCvtSW", "FF" },
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{ IROp::FCvtScaledWS, "FCvtScaledWS", "FFI" },
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{ IROp::FCvtScaledSW, "FCvtScaledSW", "FFI" },
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{ IROp::FCmp, "FCmp", "mFF" },
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{ IROp::FSat0_1, "FSat(0 - 1)", "FF" },
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{ IROp::FSatMinus1_1, "FSat(-1 - 1)", "FF" },
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{ IROp::FMovFromGPR, "FMovFromGPR", "FG" },
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{ IROp::FMovToGPR, "FMovToGPR", "GF" },
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{ IROp::OptFMovToGPRShr8, "OptFMovToGPRShr8", "GF" },
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{ IROp::OptFCvtSWFromGPR, "OptFCvtSWFromGPR", "FG" },
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{ IROp::FpCondFromReg, "FpCondFromReg", "_G" },
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{ IROp::FpCondToReg, "FpCondToReg", "G" },
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{ IROp::FpCtrlFromReg, "FpCtrlFromReg", "_G" },
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{ IROp::FpCtrlToReg, "FpCtrlToReg", "G" },
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{ IROp::VfpuCtrlToReg, "VfpuCtrlToReg", "GT" },
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{ IROp::SetCtrlVFPU, "SetCtrlVFPU", "TC" },
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{ IROp::SetCtrlVFPUReg, "SetCtrlVFPUReg", "TG" },
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{ IROp::SetCtrlVFPUFReg, "SetCtrlVFPUFReg", "TF" },
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{ IROp::FCmovVfpuCC, "FCmovVfpuCC", "FFI", IRFLAG_SRC3DST },
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{ IROp::FCmpVfpuBit, "FCmpVfpuBit", "IFF" },
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{ IROp::FCmpVfpuAggregate, "FCmpVfpuAggregate", "I" },
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{ IROp::Vec4Init, "Vec4Init", "Vv" },
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{ IROp::Vec4Shuffle, "Vec4Shuffle", "VVs" },
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{ IROp::Vec4Blend, "Vec4Blend", "VVVc" },
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{ IROp::Vec4Mov, "Vec4Mov", "VV" },
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{ IROp::Vec4Add, "Vec4Add", "VVV" },
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{ IROp::Vec4Sub, "Vec4Sub", "VVV" },
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{ IROp::Vec4Div, "Vec4Div", "VVV" },
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{ IROp::Vec4Mul, "Vec4Mul", "VVV" },
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{ IROp::Vec4Scale, "Vec4Scale", "VVF" },
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{ IROp::Vec4Dot, "Vec4Dot", "FVV" },
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{ IROp::Vec4Neg, "Vec4Neg", "VV" },
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{ IROp::Vec4Abs, "Vec4Abs", "VV" },
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// Pack/Unpack
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{ IROp::Vec2Unpack16To31, "Vec2Unpack16To31", "2F" }, // Note that the result is shifted down by 1, hence 31
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{ IROp::Vec2Unpack16To32, "Vec2Unpack16To32", "2F" },
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{ IROp::Vec4Unpack8To32, "Vec4Unpack8To32", "VF" },
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{ IROp::Vec4DuplicateUpperBitsAndShift1, "Vec4DuplicateUpperBitsAndShift1", "VV" },
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{ IROp::Vec4ClampToZero, "Vec4ClampToZero", "VV" },
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{ IROp::Vec2ClampToZero, "Vec2ClampToZero", "22" },
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{ IROp::Vec4Pack32To8, "Vec4Pack32To8", "FV" },
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{ IROp::Vec4Pack31To8, "Vec4Pack31To8", "FV" },
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{ IROp::Vec2Pack32To16, "Vec2Pack32To16", "F2" },
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{ IROp::Vec2Pack31To16, "Vec2Pack31To16", "F2" },
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{ IROp::Interpret, "Interpret", "_C", IRFLAG_BARRIER },
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{ IROp::Downcount, "Downcount", "_C" },
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{ IROp::ExitToPC, "ExitToPC", "", IRFLAG_EXIT },
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{ IROp::ExitToConst, "Exit", "C", IRFLAG_EXIT },
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{ IROp::ExitToConstIfEq, "ExitIfEq", "CGG", IRFLAG_EXIT },
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{ IROp::ExitToConstIfNeq, "ExitIfNeq", "CGG", IRFLAG_EXIT },
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{ IROp::ExitToConstIfGtZ, "ExitIfGtZ", "CG", IRFLAG_EXIT },
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{ IROp::ExitToConstIfGeZ, "ExitIfGeZ", "CG", IRFLAG_EXIT },
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{ IROp::ExitToConstIfLeZ, "ExitIfLeZ", "CG", IRFLAG_EXIT },
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{ IROp::ExitToConstIfLtZ, "ExitIfLtZ", "CG", IRFLAG_EXIT },
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{ IROp::ExitToReg, "ExitToReg", "_G", IRFLAG_EXIT },
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{ IROp::Syscall, "Syscall", "_C", IRFLAG_EXIT },
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{ IROp::Break, "Break", "", IRFLAG_EXIT },
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{ IROp::SetPC, "SetPC", "_G" },
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{ IROp::SetPCConst, "SetPC", "_C" },
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{ IROp::CallReplacement, "CallRepl", "Gr", IRFLAG_BARRIER },
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{ IROp::Breakpoint, "Breakpoint", "_C", IRFLAG_BARRIER },
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{ IROp::MemoryCheck, "MemoryCheck", "IGC", IRFLAG_BARRIER },
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{ IROp::ValidateAddress8, "ValidAddr8", "_GC", IRFLAG_BARRIER },
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{ IROp::ValidateAddress16, "ValidAddr16", "_GC", IRFLAG_BARRIER },
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{ IROp::ValidateAddress32, "ValidAddr32", "_GC", IRFLAG_BARRIER },
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{ IROp::ValidateAddress128, "ValidAddr128", "_GC", IRFLAG_BARRIER },
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{ IROp::RestoreRoundingMode, "RestoreRoundingMode", "" },
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{ IROp::ApplyRoundingMode, "ApplyRoundingMode", "" },
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{ IROp::UpdateRoundingMode, "UpdateRoundingMode", "" },
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{IROp::LogIRBlock, "LogIRBlock", ""}
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};
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const IRMeta *metaIndex[256];
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// Is there a way to constexpr this?
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void InitIR() {
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if (metaIndex[0])
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return;
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for (size_t i = 0; i < ARRAY_SIZE(irMeta); i++) {
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metaIndex[(int)irMeta[i].op] = &irMeta[i];
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}
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}
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void IRWriter::Write(IROp op, u8 dst, u8 src1, u8 src2) {
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IRInst inst;
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inst.op = op;
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inst.dest = dst;
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inst.src1 = src1;
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inst.src2 = src2;
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inst.constant = nextConst_;
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insts_.push_back(inst);
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nextConst_ = 0;
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}
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void IRWriter::WriteSetConstant(u8 dst, u32 value) {
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Write(IROp::SetConst, dst, AddConstant(value));
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}
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int IRWriter::AddConstant(u32 value) {
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nextConst_ = value;
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return 255;
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}
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int IRWriter::AddConstantFloat(float value) {
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u32 val;
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memcpy(&val, &value, 4);
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return AddConstant(val);
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}
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void IRWriter::ReplaceConstant(size_t instNumber, u32 newConstant) {
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_dbg_assert_(instNumber < insts_.size());
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insts_[instNumber].constant = newConstant;
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}
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static std::string GetGPRName(int r) {
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if (r < 32) {
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return currentDebugMIPS->GetRegName(0, r);
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}
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switch (r) {
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case IRTEMP_0: return "irtemp0";
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case IRTEMP_1: return "irtemp1";
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case IRTEMP_2: return "irtemp2";
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case IRTEMP_3: return "irtemp3";
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case IRTEMP_LHS: return "irtemp_lhs";
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case IRTEMP_RHS: return "irtemp_rhs";
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case IRTEMP_LR_ADDR: return "irtemp_addr";
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case IRTEMP_LR_VALUE: return "irtemp_value";
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case IRTEMP_LR_MASK: return "irtemp_mask";
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case IRTEMP_LR_SHIFT: return "irtemp_shift";
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default: return "(unk)";
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}
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}
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void DisassembleParam(char *buf, int bufSize, u8 param, char type, u32 constant) {
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static const char * const vfpuCtrlNames[VFPU_CTRL_MAX] = {
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"SPFX",
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"TPFX",
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"DPFX",
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"CC",
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"INF4",
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"RSV5",
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"RSV6",
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"REV",
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"RCX0",
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"RCX1",
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"RCX2",
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"RCX3",
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"RCX4",
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"RCX5",
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"RCX6",
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"RCX7",
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};
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static const char * const initVec4Names[8] = {
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"[0 0 0 0]",
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"[1 1 1 1]",
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"[-1 -1 -1 -1]",
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"[1 0 0 0]",
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"[0 1 0 0]",
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"[0 0 1 0]",
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"[0 0 0 1]",
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};
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static const char * const xyzw = "xyzw";
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switch (type) {
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case 'G':
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snprintf(buf, bufSize, "%s", GetGPRName(param).c_str());
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break;
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case 'F':
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if (param >= 32) {
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snprintf(buf, bufSize, "vf%d", param - 32);
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} else {
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snprintf(buf, bufSize, "f%d", param);
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}
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break;
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case 'V':
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if (param >= 32) {
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snprintf(buf, bufSize, "vf%d..vf%d", param - 32, param - 32 + 3);
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} else {
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snprintf(buf, bufSize, "f%d..f%d", param, param + 3);
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}
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break;
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case '2':
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if (param >= 32) {
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snprintf(buf, bufSize, "vf%d,vf%d", param - 32, param - 32 + 1);
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} else {
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snprintf(buf, bufSize, "f%d,f%d", param, param + 1);
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}
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break;
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case 'C':
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snprintf(buf, bufSize, "0x%08x", constant);
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break;
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case 'c':
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snprintf(buf, bufSize, "0x%02x", constant);
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break;
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case 'I':
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snprintf(buf, bufSize, "0x%02x", param);
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break;
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case 'm':
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snprintf(buf, bufSize, "%d", param);
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break;
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case 'T':
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snprintf(buf, bufSize, "%s", vfpuCtrlNames[param]);
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break;
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case 'v':
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snprintf(buf, bufSize, "%s", initVec4Names[param]);
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break;
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case 's':
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snprintf(buf, bufSize, "%c%c%c%c", xyzw[param & 3], xyzw[(param >> 2) & 3], xyzw[(param >> 4) & 3], xyzw[(param >> 6) & 3]);
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break;
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case 'r':
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{
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const ReplacementTableEntry *entry = GetReplacementFunc(constant);
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if (entry) {
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snprintf(buf, bufSize, "%s", entry->name);
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} else {
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snprintf(buf, bufSize, "(unkn. repl %d)", constant);
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}
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break;
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}
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case '_':
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case '\0':
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buf[0] = 0;
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break;
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default:
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snprintf(buf, bufSize, "?");
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break;
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}
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}
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const IRMeta *GetIRMeta(IROp op) {
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return metaIndex[(int)op];
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}
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void DisassembleIR(char *buf, size_t bufsize, IRInst inst) {
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const IRMeta *meta = GetIRMeta(inst.op);
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if (!meta) {
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snprintf(buf, bufsize, "Unknown %d", (int)inst.op);
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return;
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}
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char bufDst[16];
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char bufSrc1[16];
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char bufSrc2[16];
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// Only really used for constant.
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char bufSrc3[16];
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DisassembleParam(bufDst, sizeof(bufDst) - 2, inst.dest, meta->types[0], inst.constant);
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DisassembleParam(bufSrc1, sizeof(bufSrc1) - 2, inst.src1, meta->types[1], inst.constant);
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DisassembleParam(bufSrc2, sizeof(bufSrc2), inst.src2, meta->types[2], inst.constant);
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DisassembleParam(bufSrc3, sizeof(bufSrc3), inst.src3, meta->types[3], inst.constant);
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if (meta->types[1] && meta->types[0] != '_') {
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strcat(bufDst, ", ");
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}
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if (meta->types[2] && meta->types[1] != '_') {
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strcat(bufSrc1, ", ");
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}
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if (meta->types[3] && meta->types[2] != '_') {
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strcat(bufSrc2, ", ");
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}
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snprintf(buf, bufsize, "%s %s%s%s%s", meta->name, bufDst, bufSrc1, bufSrc2, bufSrc3);
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}
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