mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
233 lines
6.8 KiB
C++
233 lines
6.8 KiB
C++
// Copyright (c) 2022- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include <cstdint>
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#include "Common/CodeBlock.h"
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#include "Common/Common.h"
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namespace RiscVGen {
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enum RiscVReg {
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X0 = 0, X1, X2, X3, X4, X5, X6, X7,
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X8, X9, X10, X11, X12, X13, X14, X15,
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X16, X17, X18, X19, X20, X21, X22, X23,
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X24, X25, X26, X27, X28, X29, X30, X31,
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R_ZERO = 0,
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R_RA = 1,
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R_SP = 2,
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R_GP = 3,
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R_TP = 4,
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R_FP = 8,
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F0 = 0x20, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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F24, F25, F26, F27, F28, F29, F30, F31,
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};
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enum class FixupBranchType {
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B,
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J,
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};
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enum class Fence {
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I = 0b1000,
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O = 0b0100,
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R = 0b0010,
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W = 0b0001,
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RW = R | W,
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IO = I | O,
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};
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ENUM_CLASS_BITOPS(Fence);
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struct FixupBranch {
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FixupBranch(const u8 *p, FixupBranchType t) : ptr(p), type(t) {}
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const u8 *ptr;
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FixupBranchType type;
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};
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class RiscVEmitter {
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public:
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RiscVEmitter() {}
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RiscVEmitter(const u8 *codePtr, u8 *writablePtr);
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virtual ~RiscVEmitter() {}
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void SetCodePointer(const u8 *ptr, u8 *writePtr);
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const u8 *GetCodePointer() const;
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u8 *GetWritableCodePtr();
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void ReserveCodeSpace(u32 bytes);
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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void FlushIcache();
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void FlushIcacheSection(const u8 *start, const u8 *end);
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void SetJumpTarget(const FixupBranch &branch);
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bool BInRange(const void *func) const;
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bool JInRange(const void *func) const;
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void LUI(RiscVReg rd, s32 simm32);
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void AUIPC(RiscVReg rd, s32 simm32);
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void JAL(RiscVReg rd, const void *dst);
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void JALR(RiscVReg rd, RiscVReg rs1, s32 simm12);
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FixupBranch JAL(RiscVReg rd);
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// Psuedo-instructions for convenience/clarity.
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void J(const void *dst) {
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JAL(R_ZERO, dst);
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}
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void JR(RiscVReg rs1, u32 simm12 = 0) {
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JALR(R_ZERO, rs1, simm12);
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}
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void RET() {
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JR(R_RA);
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}
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FixupBranch J() {
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return JAL(R_ZERO);
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}
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void BEQ(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BNE(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BLT(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BGE(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BLTU(RiscVReg rs1, RiscVReg rs2, const void *dst);
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void BGEU(RiscVReg rs1, RiscVReg rs2, const void *dst);
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FixupBranch BEQ(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BNE(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BLT(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BGE(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BLTU(RiscVReg rs1, RiscVReg rs2);
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FixupBranch BGEU(RiscVReg rs1, RiscVReg rs2);
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void LB(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void LH(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void LW(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void LBU(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void LHU(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SB(RiscVReg rs2, RiscVReg rs1, s32 simm12);
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void SH(RiscVReg rs2, RiscVReg rs1, s32 simm12);
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void SW(RiscVReg rs2, RiscVReg rs1, s32 simm12);
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void ADDI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SLTI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SLTIU(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void XORI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void ORI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void ANDI(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void NOP() {
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ADDI(R_ZERO, R_ZERO, 0);
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}
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void MV(RiscVReg rd, RiscVReg rs1) {
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ADDI(rd, rs1, 0);
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}
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void NOT(RiscVReg rd, RiscVReg rs1) {
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XORI(rd, rs1, -1);
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}
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void SLLI(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRLI(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRAI(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void ADD(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SUB(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLT(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLTU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void XOR(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRA(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void OR(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void AND(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void NEG(RiscVReg rd, RiscVReg rs) {
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SUB(rd, R_ZERO, rs);
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}
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void FENCE(Fence predecessor, Fence successor);
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void FENCE_TSO();
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void ECALL();
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void EBREAK();
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// 64-bit instructions - oens ending in W sign extend result to 32 bits.
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void LWU(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void LD(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SD(RiscVReg rs2, RiscVReg rs1, s32 simm12);
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void ADDIW(RiscVReg rd, RiscVReg rs1, s32 simm12);
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void SLLIW(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRLIW(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void SRAIW(RiscVReg rd, RiscVReg rs1, u32 shamt);
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void ADDW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SUBW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SLLW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRLW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void SRAW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void NEGW(RiscVReg rd, RiscVReg rs) {
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SUBW(rd, R_ZERO, rs);
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}
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// Integer multiplication and division.
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void MUL(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void MULH(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void MULHSU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void MULHU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIV(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIVU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REM(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REMU(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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// 64-bit only multiply and divide.
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void MULW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIVW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void DIVUW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REMW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void REMUW(RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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private:
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void SetJumpTarget(const FixupBranch &branch, const void *dst);
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bool BInRange(const void *src, const void *dst) const;
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bool JInRange(const void *src, const void *dst) const;
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inline void Write32(u32 value) {
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*(u32 *)writable_ = value;
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code_ += 4;
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writable_ += 4;
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}
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inline void Write16(u16 value) {
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*(u16 *)writable_ = value;
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code_ += 2;
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writable_ += 2;
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}
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const u8 *code_ = nullptr;
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u8 *writable_ = nullptr;
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const u8 *lastCacheFlushEnd_ = nullptr;
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};
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class MIPSCodeBlock : public CodeBlock<RiscVEmitter> {
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private:
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void PoisonMemory(int offset) override;
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};
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};
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