mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
e0afdfe9be
If stepping, we may get into a delay slot within interpreted code, and then try to run (i.e. Step Out), which won't clear the delay slot properly. This can cause weird behavior when interp is used again later, in addition to immediate wrong branching behavior.
338 lines
8.2 KiB
C++
338 lines
8.2 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <cmath>
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#include <limits>
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#include "Common/Math/math_util.h"
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#include "Common.h"
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#include "Common/Serialize/Serializer.h"
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#include "Common/Serialize/SerializeFuncs.h"
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#include "Core/ConfigValues.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/MIPSDebugInterface.h"
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#include "Core/MIPS/MIPSVFPUUtils.h"
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#include "Core/MIPS/IR/IRJit.h"
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#include "Core/Reporting.h"
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#include "Core/System.h"
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#include "Core/HLE/sceDisplay.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "Core/CoreTiming.h"
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MIPSState mipsr4k;
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MIPSState *currentMIPS = &mipsr4k;
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MIPSDebugInterface debugr4k(&mipsr4k);
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MIPSDebugInterface *currentDebugMIPS = &debugr4k;
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u8 voffset[128];
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u8 fromvoffset[128];
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#ifndef M_LOG2E
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#define M_E 2.71828182845904523536f
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#define M_LOG2E 1.44269504088896340736f
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#define M_LOG10E 0.434294481903251827651f
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#define M_LN2 0.693147180559945309417f
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#define M_LN10 2.30258509299404568402f
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#undef M_PI
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#define M_PI 3.14159265358979323846f
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#ifndef M_PI_2
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#define M_PI_2 1.57079632679489661923f
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#endif
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#define M_PI_4 0.785398163397448309616f
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#define M_1_PI 0.318309886183790671538f
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#define M_2_PI 0.636619772367581343076f
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#define M_2_SQRTPI 1.12837916709551257390f
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#define M_SQRT2 1.41421356237309504880f
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#define M_SQRT1_2 0.707106781186547524401f
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#endif
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const float cst_constants[32] = {
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0,
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std::numeric_limits<float>::max(), // all these are verified on real PSP
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sqrtf(2.0f),
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sqrtf(0.5f),
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2.0f/sqrtf((float)M_PI),
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2.0f/(float)M_PI,
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1.0f/(float)M_PI,
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(float)M_PI/4,
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(float)M_PI/2,
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(float)M_PI,
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(float)M_E,
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(float)M_LOG2E,
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(float)M_LOG10E,
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(float)M_LN2,
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(float)M_LN10,
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2*(float)M_PI,
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(float)M_PI/6,
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log10f(2.0f),
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logf(10.0f)/logf(2.0f),
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sqrtf(3.0f)/2.0f,
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};
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MIPSState::MIPSState() {
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MIPSComp::jit = 0;
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// Initialize vorder
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// This reordering of the VFPU registers in RAM means that instead of being like this:
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// 0x00 0x20 0x40 0x60 -> "columns", the most common direction
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// 0x01 0x21 0x41 0x61
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// 0x02 0x22 0x42 0x62
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// 0x03 0x23 0x43 0x63
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// 0x04 0x24 0x44 0x64
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// 0x06 0x26 0x45 0x65
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// ....
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// the VPU registers are effectively organized like this:
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// 0x00 0x01 0x02 0x03
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// 0x04 0x05 0x06 0x07
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// 0x08 0x09 0x0a 0x0b
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// ....
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// This is because the original indices look like this:
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// 0XXMMMYY where M is the matrix number.
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// We will now map 0YYMMMXX to 0MMMXXYY.
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// Advantages:
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// * Columns can be flushed and reloaded faster "at once"
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// * 4x4 Matrices are contiguous in RAM, making them, too, fast-loadable in NEON
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// Disadvantages:
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// * Extra indirection, can be confusing and slower (interpreter only)
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// * Flushing and reloading row registers is now slower
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int i = 0;
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for (int m = 0; m < 8; m++) {
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for (int y = 0; y < 4; y++) {
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for (int x = 0; x < 4; x++) {
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voffset[m * 4 + x * 32 + y] = i++;
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}
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}
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}
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// And the inverse.
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for (int i = 0; i < 128; i++) {
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fromvoffset[voffset[i]] = i;
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}
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// Sanity check that things that should be ordered are ordered.
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static const u8 firstThirtyTwo[] = {
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0x0, 0x20, 0x40, 0x60,
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0x1, 0x21, 0x41, 0x61,
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0x2, 0x22, 0x42, 0x62,
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0x3, 0x23, 0x43, 0x63,
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0x4, 0x24, 0x44, 0x64,
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0x5, 0x25, 0x45, 0x65,
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0x6, 0x26, 0x46, 0x66,
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0x7, 0x27, 0x47, 0x67,
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};
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for (int i = 0; i < (int)ARRAY_SIZE(firstThirtyTwo); i++) {
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if (voffset[firstThirtyTwo[i]] != i) {
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ERROR_LOG(CPU, "Wrong voffset order! %i: %i should have been %i", firstThirtyTwo[i], voffset[firstThirtyTwo[i]], i);
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}
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}
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}
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MIPSState::~MIPSState() {
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Shutdown();
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}
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void MIPSState::Shutdown() {
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if (MIPSComp::jit) {
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delete MIPSComp::jit;
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MIPSComp::jit = 0;
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}
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}
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void MIPSState::Reset() {
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Shutdown();
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Init();
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}
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void MIPSState::Init() {
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memset(r, 0, sizeof(r));
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memset(f, 0, sizeof(f));
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memset(v, 0, sizeof(v));
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memset(vfpuCtrl, 0, sizeof(vfpuCtrl));
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vfpuCtrl[VFPU_CTRL_SPREFIX] = 0xe4; //passthru
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vfpuCtrl[VFPU_CTRL_TPREFIX] = 0xe4; //passthru
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vfpuCtrl[VFPU_CTRL_DPREFIX] = 0;
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vfpuCtrl[VFPU_CTRL_CC] = 0x3f;
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vfpuCtrl[VFPU_CTRL_INF4] = 0;
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vfpuCtrl[VFPU_CTRL_REV] = 0x7772ceab;
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vfpuCtrl[VFPU_CTRL_RCX0] = 0x3f800001;
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vfpuCtrl[VFPU_CTRL_RCX1] = 0x3f800002;
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vfpuCtrl[VFPU_CTRL_RCX2] = 0x3f800004;
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vfpuCtrl[VFPU_CTRL_RCX3] = 0x3f800008;
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vfpuCtrl[VFPU_CTRL_RCX4] = 0x3f800000;
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vfpuCtrl[VFPU_CTRL_RCX5] = 0x3f800000;
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vfpuCtrl[VFPU_CTRL_RCX6] = 0x3f800000;
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vfpuCtrl[VFPU_CTRL_RCX7] = 0x3f800000;
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pc = 0;
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hi = 0;
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lo = 0;
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fpcond = 0;
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fcr31 = 0;
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debugCount = 0;
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currentMIPS = this;
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inDelaySlot = false;
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llBit = 0;
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nextPC = 0;
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downcount = 0;
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// Initialize the VFPU random number generator with .. something?
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rng.Init(0x1337);
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if (PSP_CoreParameter().cpuCore == CPUCore::JIT) {
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MIPSComp::jit = MIPSComp::CreateNativeJit(this);
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} else if (PSP_CoreParameter().cpuCore == CPUCore::IR_JIT) {
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MIPSComp::jit = new MIPSComp::IRJit(this);
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} else {
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MIPSComp::jit = nullptr;
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}
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}
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bool MIPSState::HasDefaultPrefix() const {
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return vfpuCtrl[VFPU_CTRL_SPREFIX] == 0xe4 && vfpuCtrl[VFPU_CTRL_TPREFIX] == 0xe4 && vfpuCtrl[VFPU_CTRL_DPREFIX] == 0;
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}
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void MIPSState::UpdateCore(CPUCore desired) {
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if (PSP_CoreParameter().cpuCore == desired) {
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return;
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}
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PSP_CoreParameter().cpuCore = desired;
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switch (PSP_CoreParameter().cpuCore) {
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case CPUCore::JIT:
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INFO_LOG(CPU, "Switching to JIT");
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if (MIPSComp::jit) {
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delete MIPSComp::jit;
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}
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MIPSComp::jit = MIPSComp::CreateNativeJit(this);
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break;
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case CPUCore::IR_JIT:
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INFO_LOG(CPU, "Switching to IRJIT");
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if (MIPSComp::jit) {
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delete MIPSComp::jit;
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}
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MIPSComp::jit = new MIPSComp::IRJit(this);
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break;
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case CPUCore::INTERPRETER:
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INFO_LOG(CPU, "Switching to interpreter");
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delete MIPSComp::jit;
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MIPSComp::jit = 0;
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break;
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}
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}
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void MIPSState::DoState(PointerWrap &p) {
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auto s = p.Section("MIPSState", 1, 3);
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if (!s)
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return;
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// Reset the jit if we're loading.
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if (p.mode == p.MODE_READ)
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Reset();
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if (MIPSComp::jit)
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MIPSComp::jit->DoState(p);
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else
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MIPSComp::DoDummyJitState(p);
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DoArray(p, r, sizeof(r) / sizeof(r[0]));
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DoArray(p, f, sizeof(f) / sizeof(f[0]));
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if (s <= 2) {
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float vtemp[128];
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DoArray(p, vtemp, sizeof(v) / sizeof(v[0]));
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for (int i = 0; i < 128; i++) {
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v[voffset[i]] = vtemp[i];
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}
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} else {
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DoArray(p, v, sizeof(v) / sizeof(v[0]));
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}
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DoArray(p, vfpuCtrl, sizeof(vfpuCtrl) / sizeof(vfpuCtrl[0]));
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Do(p, pc);
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Do(p, nextPC);
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Do(p, downcount);
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// Reversed, but we can just leave it that way.
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Do(p, hi);
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Do(p, lo);
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Do(p, fpcond);
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if (s <= 1) {
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u32 fcr0_unused = 0;
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Do(p, fcr0_unused);
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}
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Do(p, fcr31);
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Do(p, rng.m_w);
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Do(p, rng.m_z);
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Do(p, inDelaySlot);
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Do(p, llBit);
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Do(p, debugCount);
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if (p.mode == p.MODE_READ && MIPSComp::jit) {
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// Now that we've loaded fcr31, update any jit state associated.
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MIPSComp::jit->UpdateFCR31();
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}
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}
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void MIPSState::SingleStep() {
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int cycles = MIPS_SingleStep();
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currentMIPS->downcount -= cycles;
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CoreTiming::Advance();
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}
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// returns 1 if reached ticks limit
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int MIPSState::RunLoopUntil(u64 globalTicks) {
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switch (PSP_CoreParameter().cpuCore) {
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case CPUCore::JIT:
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case CPUCore::IR_JIT:
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while (inDelaySlot) {
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// We must get out of the delay slot before going into jit.
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SingleStep();
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}
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MIPSComp::jit->RunLoopUntil(globalTicks);
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break;
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case CPUCore::INTERPRETER:
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return MIPSInterpret_RunUntil(globalTicks);
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}
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return 1;
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}
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void MIPSState::InvalidateICache(u32 address, int length) {
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// Only really applies to jit.
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if (MIPSComp::jit)
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MIPSComp::jit->InvalidateCacheAt(address, length);
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}
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void MIPSState::ClearJitCache() {
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if (MIPSComp::jit)
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MIPSComp::jit->ClearCache();
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}
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