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ppsspp/Core/MIPS/RiscV
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Unknown W. Brackets 00c80cea6e irjit: Optimize offset logging during compile. 
As I guessed, this was expensive.  using a vector and reserve isn't very.
It's nice to keep this before logBlocks_ is > 0, in case it's set mid
block.
2023-09-30 15:56:18 -07:00
..
RiscVAsm.cpp IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
RiscVCompALU.cpp riscv: Use a single reg for LO/HI. 2023-08-20 14:49:09 -07:00
RiscVCompBranch.cpp x86jit: Stub out op categories to files. 2023-08-20 22:28:54 -07:00
RiscVCompFPU.cpp IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
RiscVCompLoadStore.cpp irjit: Fix safety of kernel bit memory addresses. 2023-09-24 10:18:55 -07:00
RiscVCompSystem.cpp IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
RiscVCompVec.cpp arm64jit: Implement Vec4Blend. 2023-09-05 00:10:26 -07:00
RiscVJit.cpp irjit: Optimize offset logging during compile. 2023-09-30 15:56:18 -07:00
RiscVJit.h IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
RiscVRegCache.cpp irjit: Add facility for native reg transfer. 2023-09-24 16:28:29 -07:00
RiscVRegCache.h irjit: Add facility for native reg transfer. 2023-09-24 16:28:29 -07:00